Semiconductor field region implant methodology

Details Semiconductor field region implant methodology Semiconductor field region implant methodology

1995-08-02

2002-11-19

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

Reexamination Certificate

active

06482719

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor processing and more particularly to a p-type field region implant which substantially maintains its position during subsequent temperature cycles relative to adjacent n-type source and drain regions.
2. Description of the Relevant Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline material or “polysilicon” material over a relatively thin gate oxide, and implanting the polysilicon and adjacent source/drain regions with an impurity dopant material. If the impurity dopant material is n-type, then the resulting MOSFET is an NMOSFET (“NMOS”) device. Conversely, if the impurity dopant material is p-type, then the resulting MOSFET device is a PMOSFET (“PMOS”) device.
There are numerous MOSFETs devices spaced across a single piece of silicon. Each device must be electrically isolated from other devices. Generally speaking, MOSFETS are self-isolated, as long as the source-substrate and drain-substrate pn junctions are held in reverse bias. The self-isolation property of MOSFETs devices represents a substantial area savings for NMOS and PMOS circuits compared to junction-isolated bipolar circuits.
Once the NMOS (and/or PMOS) devices are formed in silicon, they must then be interconnected by metal conductors placed across oxide in regions between the devices. Oxide formed between active devices is generally referred to as “field oxide”. Field oxide is distinguishable from “gate oxide” in that gate oxide is formed in the active regions between source and drain and between polysilicon gate and underlying silicon.
The metal or poly conductors extending over field oxide often carry significant voltage levels. It is important that the conductor voltage not activate the parasitic channel regions underlying field oxide. The threshold voltage in the field region underlying the field oxides must therefore be kept higher than any possible operating voltage on the overlying conductors. One way in which to prevent channels in the field region. is to increase the thickness of the field oxide. Unfortunately, thick field oxide can present large disparities in the upper surface elevation leading to poor planarization and possible step coverage problems. Another, more suitable way in which to maximize field region threshold voltage is to implant the field region prior to field oxide growth. The field region can be implanted with a dopant type matching that of the underlying substrate (or tub). Implantation of the field region is often referred to as “channel-stop implant”. The combination of channel-stop implant with adequate field oxide thickness can provide isolation for PMOS or NMOS devices to prevent channel formation in the field region.
The field oxide must be selectively grown only in the field regions and not in the active regions in which the active channels of the MOSFETs are formed. A popular method in which to selectively grow field oxide is often referred to as local oxidation of silicon (“LOCOS”). LOCOS methodology begins by covering the active regions with a thin layer of silicon nitride which prevents oxidation from occurring beneath the nitride. After the nitride layer has been etched away in the field regions, and prior to field oxide growth, the silicon in the field regions is selectively implanted with the channel-stop dopant. Thus, the field or channel-stop region becomes self-aligned to the field oxide.
Growth of field oxide can often present step-coverage limitation, and can be overcome to some degree by a selective oxidation approach. If the silicon is etched after the nitride layer is patterned, the field oxide can then be grown until it forms a planar surface with the silicon substrate. Etch-back of silicon in the field regions is often referred to as the “fully recessed” isolation oxide process. If the field oxide is grown without prior etch-back, the resulting field oxide will only be “partially (or semi) recessed”. In the semi recessed process, the field oxide step height is larger than in the fully recessed process, but nonetheless, has a gentle upward slope from the silicon juncture area, some of which is consumed by oxide growth. Consumption of silicon during oxide growth provides a gentle upward slope at the outer edge of the areas in which nitride is removed. Thus, the edges of the field oxide slope upward at their juncture with the edge of the nitride layer.
While channel-stop implant in the field region is necessary to prevent channel formation therein, conventional channel-stop implant can, in and of itself, present problems. In NMOS circuits, a p-type implant of boron is generally used in the field region. After field oxide growth, boron is supposed to reside primarily below the field oxide. Unfortunately, due to the high diffusivity of boron (i.e., due to its small atomic weight and size), implanted boron atoms readily segregate and move laterally toward adjacent arsenic-implanted source and drain regions. Boron atoms may also diffuse into the growing field oxide or deeper within the substrate. Lateral (diffusion parallel to the substrate upper surface) or non-lateral (diffusion perpendicular to the substrate upper surface) is primarily caused by heat cycles occurring after boron is initially placed. Heat cycles occur during field oxide growth and are a necessary part of that growth.
Any segregation or diffusion of boron from its implanted area laterally to adjacent n-type (arsenic) source and drain regions can cause high source/drain-to-substrate (or tub) capacitances and/or reduction in source/drain-to-substrate (or tub) n+p junction breakdown voltages. See, e.g., Wolf, “Silicon Processing for the VLSI Era”, Volume 2: Process Integration (Lattice Press, 1990), pp. 20-22. Generally speaking, breakdown voltage is inversely proportional to the doping concentration of the lighter-doped side of the p+n junction. Thus, increasing the doping of the p-type substrate (or tub) will reduce the breakdown voltage of the n-type source and drain regions adjoining the substrate. Source/drain-to-substrate capacitances are directly proportional to the doping concentration of the lighter-doped side. Increasing the doping of the p-type substrate will increase the parasitic capacitance of the source and drain regions leading to slower operation.
As described in Wolf, conventional research into minimizing lateral and non-lateral diffusion has focused primarily upon the field oxide step. Using high pressure oxidation (“HIPOX”) to grow the field oxide allows the oxide growth temperature to be reduced thereby reducing the diffusion length of boron. Research effort has also focused upon co-implanting germanium ions with boron ions to exploit the fact that boron diffuses with a low diffusivity in the presence of implanted germanium. By lowering the growth temperature of field oxide and/or co-implanting germanium with boron, research appears to indicate an increase in field threshold voltage with the same or lower dosage of boron.
Instead of merely depositing boron at high concentrations necessary to offset any lateral diffusions or at deep depths in order for the ions not to be absorbed by the growing field oxide, researchers point to changing the field oxide growth step or co-implanting germanium. Using HIPOX to grow the field oxide requires the oxide growth chamber be retrofitted with pressure equipment. Retrofitting the oxide chamber can oftentimes be costly. Moreover, each wafer run requires the oxide chamber to be pressurized and then de-pressurized leading to lower wafer throughput. If the chamber is under pressure during oxide growth, disturbance of and ingress of unwanted particles can occur. Still further, if germanium is co-implanted with boron, boron must be implanted as the source material followed by germanium implantation. The two step implant process can further decrease wafer throughput and add to the complexity of implant source retrofit.
It would be advantageous to avoid retrofit of the wa

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