Semiconductor fabrication having multi-level transistors and hig

Details Semiconductor fabrication having multi-level transistors and hig Semiconductor fabrication having multi-level transistors and hig

1997-05-02

1999-07-20

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438618, H01L 21336

Patent

active

059267003

ABSTRACT:
An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure. Select portions of the primary and secondary interlevel dielectrics are then removed to expose one of the junctions and a portion of the doped polysilicon structure arranged proximate this junction. An interconnect is formed contiguously between the junction and the polysilicon structure by depositing a conductive material within the removed portions.

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