Semiconductor fabrication employing a transistor gate coupled to

Details Semiconductor fabrication employing a transistor gate coupled to Semiconductor fabrication employing a transistor gate coupled to

1997-10-14

1999-08-24

Fourson, George R.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438153, 438219, 438295, 438405, H01L 21336, H01L 21762

Patent

active

059435623

ABSTRACT:
A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures. Dielectric spacers are formed upon the opposed sidewall surfaces of the gate conductor, and S/D regions are formed within the second substrate. The S/D implant is self-aligned to the exposed lateral edges of the dielectric spacers. The resulting transistor may be switched on quickly and has reduced current leakage in the off state. Transistors formed within and upon the first substrate are isolated from noise which may be induced in the second substrate.

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