Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-10-15
2004-07-06
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C414S940000, C700S121000
Reexamination Certificate
active
06759256
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The present document is based on Japanese Priority Document JP 2001-322072, filed in the Japanese Patent Office on Oct. 19, 2001, the entire contents of which being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices by submitting, for example, semiconductor wafers to various semiconductor fabricating processes.
2. Background of Related Art
Semiconductor device fabrication involves patterning a semiconductor wafer via a thin film forming technique, such as evaporation or sputtering, to form many circuits on the wafer, and then dicing the patterned wafer into many semiconductor chips.
During the fabrication, inspection is performed by transfer of semiconductor wafers to inspection equipment between processes in order to manufacture high-quality products at high yield.
In a typical semiconductor fabricating practice, the processes are carried out on a cassette basis, with each cassette accommodating, for example, 25 (twenty-five) semiconductor wafers. Thus, once a process is finished, the 25 wafers are transferred en bloc as accommodated in the cassette to the inspection equipment for diagnosis.
FIG. 9
shows a flow of steps included in a conventional lithographic process.
First, in step ST
101
, a cassette in which a plurality of semiconductor wafers are accommodated is mounted on a loader/unloader of an in-line stepper used in the lithographic process.
Next, in step ST
102
, the in-line stepper submits these wafers to the lithographic process including resist coating, exposure and development, and then returns the resultant wafers to where they were in the cassette in order of their submission to the process.
The cassette is then delivered to inspection apparatuses, where the lithographically processed wafers have their pattern accuracy measured with a scanning electron microscope (SEM) (step ST
104
), their overlay accuracy evaluated (step ST
105
), and their surface visually checked to locate any damage thereon (step ST
106
).
Thus, the lithography process, among other semiconductor fabricating processes, involves a number of inspections including pattern accuracy, overlay accuracy and wafer surface visual checkup which demand time, sometimes longer than the lithography process itself.
However, in performing the inspections, the above conventional lithographic process, because of its cassette-based serial operation, prevents transfer of any wafer to the inspection apparatuses unless the lithographic process is completed for all the wafers in the cassette, thus making the process time-consuming.
In addition, this time-consuming cassette-based serial operation would greatly discourage productivity increase when combined with commonly practiced sampling inspection in which some of semiconductor wafers in a cassette are selected for inspection.
To overcome these problems, proposed to date are an in-line approach in which semiconductor fabricating apparatuses and inspection apparatuses are grouped in-line into a semiconductor fabricating system, and a monitoring approach in which inspection units are incorporated into semiconductor fabricating apparatuses.
However, the in-line approach is unable to balance varying throughputs among the apparatuses involved nor is it cost-effective, in consideration of factors such as sampling inspection being involved and the apparatuses being sensitive to external vibrations, etc. The monitoring approach would also be premature because individual element technologies currently available for semiconductor fabrication would be incompetent in accommodating inspection needs for high-volume production.
The fact that a number of steps, such as wafer surface checkup depends on visual inspection by a checker, is one major reason why the inspection is carried out after completion of the semiconductor fabrication process for all semiconductor wafers as described above.
SUMMARY OF THE INVENTION
The present invention solves the above and other problems by providing a semiconductor fabricating method capable of wafer inspection simultaneously with submission of semiconductor wafers to a semiconductor fabricating process to improve throughput, quality and yield.
In a first embodiment, the method of the present invention is carried out as follows. A first container accommodating a predetermined number of semiconductor wafers and labeled with a first identifier and a second container labeled with a second identifier are mounted on a first processing apparatus, and the first and second identifiers are stored.
While the first processing apparatus is submitting the semiconductor wafers to a first process, designated ones of semiconductor wafers on which the first process is performed are loaded into the second container as sample wafers. (Hereafter, the wafer for inspection is called a sample wafer).
The second container is mounted on an inspection apparatus to inspect the sample wafers.
The first container accommodating a rest of the processed semiconductor wafers after the first process is performed and the second container accommodating the inspected sample wafers are mounted on a second processing apparatus after the inspected sample wafers are judged to be acceptable, and the first and second containers mounted on the second processing apparatus are identified by comparison of identifiers thereof with the stored first and second identifiers, respectively.
The second processing apparatus submits the rest of the processed semiconductor wafers after the first process is performed and the inspected sample wafers to a second process, and the processed sample wafers by submission to the second process are returned to the first container.
In the step of loading designated ones of the processed semiconductor wafers into the second container as sample wafers, position information about where the sample wafers have been accommodated in the first container may be stored in association with the stored first and second identifiers of said first and second containers, and in the step of returning the inspected sample wafers to the first container, the stored position information based on the identifying of the second and first containers maybe read to return the inspected sample wafers to an original position in the first container.
In the step of inspecting the sample wafers, the identifier of the second container mounted on the inspection apparatus may be identified by comparison of the stored second identifier thereof with the second identifier and inspection results of the inspected sample wafers as inspection results of the processed semiconductor wafers accommodated in the first container may be stored.
According to this embodiment, the identifiers of the respective containers are stored before processing, and while the first processing apparatus is submitting the semiconductor wafers to the first process, some processed wafers are loaded into the second container as sample wafers. Then, these sample wafers are inspected by the inspection apparatus while the rest of the semiconductor wafers in the first container are continuously submitted to the first process.
When the inspected wafers are found to be acceptable, both the first container accommodating the rest of the semiconductor wafers for which the first process has finished, and the second container accommodating the inspected sample wafers are mounted on the second processing apparatus for subsequent processing.
During the mounting, the first and second containers mounted on the second processing apparatus are identified by comparing identifiers thereof with the previously stored identifiers, respectively, to confirm that the sample wafers have been taken out of the first container.
The second processing apparatus submits the rest of the semiconductor wafers and the sample wafers to the second process, and the processed sample wafers are put back to the first container, whereby the predetermined number of semiconductor wafers is back in the first container.
Depke Robert J.
Holland & Knight LLP
Jr. Carl Whitehead
Smoot Stephen W.
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