Semiconductor dynamic random access memory

Static information storage and retrieval – Read/write circuit – Signals

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365233, 365236, G11C 11413

Patent

active

055218733

ABSTRACT:
A DRAM provided with special function modes of a plurality of different types and capable of discriminating the modes and entering a selected one thereof without conflicting with a conventional standardized WCBR entry method. Such a DRAM comprises a counter circuit FF for counting the number of times a /WE signal is made active while a /RAS signal is active after the start of a /WCBR cycle and an entry circuit that discriminates the special function modes and enters the DRAM in a selected one thereof according to the obtained count.

REFERENCES:
patent: 4811299 (1989-03-01), Miyazawa et al.
patent: 5285409 (1994-02-01), Hwangbo et al.
Kraus et al., "Design for Test of Mbit DRAMs", 1989 International Test Conference Proceedings, Washington D.C., pp. 316-321, Aug. 1989.

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