Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1986-07-09
1988-11-22
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365230, G11C 800, G11C 700
Patent
active
047870672
ABSTRACT:
A semiconductor dynamic memory device having an improved refreshing time is disclosed wherein the memory device provides two buffer memories exclusively for the external and refresh addresses, each of the buffer memories comprising a preamplifier and a driver stage. When the falling edge of a RAS signal is detected, all the circuits are enabled in parallel, but the operation of the driver is suppressed. As soon as a CAS before RAS detector discriminates which of the falling edges of the CAS and RAS signals becomes low earlier, it sends an address driving signal to one of the drivers, and the external address or refresh address are sent immediately. Using this technique, the prior art sequential operation of discriminating the falling edges of RAS and CAS signal, sending the refresh signal, receiving it and switching the circuit from external address to refresh address is eliminated, and is replaced by a parallel operation. Thus the set up time of the dynamic memory is reduced to 1-2 n.sec. by the present invention.
REFERENCES:
patent: 4079462 (1978-03-01), Koo
patent: 4646272 (1987-02-01), Takasugi
patent: 4653030 (1987-03-01), Tachibana et al.
Kodama Nobumi
Nakano Masao
Sato Kimiaki
Takemae Yoshihiro
Fujitsu Limited
Gossage Glenn A.
Hecker Stuart N.
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