Semiconductor die with reduced bump-to-pad ratio

Details Semiconductor die with reduced bump-to-pad ratio Semiconductor die with reduced bump-to-pad ratio

2007-01-18

2010-02-16

Toledo, Fernando L (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S777000, C257SE23010, C257S686000

Reexamination Certificate

active

07663235

ABSTRACT:
According to one exemplary embodiment, a semiconductor die includes at least one pad ring situated on an active surface of the semiconductor die, where the at least one pad ring includes a number of pads. The semiconductor die further includes a number of bumps including at least one shared bump. The at least one shared bump is shared by at least two pads, thereby causing the number of bumps to be fewer than the number of pads. The at least two pads can be at least two ground pads, at least two power pads, or at least two reference voltage pads.

REFERENCES:
patent: 6472745 (2002-10-01), Iizuka
patent: 6511901 (2003-01-01), Lam et al.
patent: 6534853 (2003-03-01), Liu et al.
patent: 2003/0183928 (2003-10-01), Miyazawa
patent: 2005/0280127 (2005-12-01), Zhao et al.

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