Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2011-01-11
2011-01-11
Pham, Thanhha (Department: 2894)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S033000, C438S068000, C257SE21599
Reexamination Certificate
active
07867825
ABSTRACT:
A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.
REFERENCES:
patent: 6538301 (2003-03-01), Yamada et al.
patent: 6566735 (2003-05-01), Minn et al.
patent: 2003/0162369 (2003-08-01), Kobayashi
patent: 2003/0193090 (2003-10-01), Otani et al.
patent: 2005/0269702 (2005-12-01), Otsuka
patent: 00122737 (1983-07-01), None
patent: 406151584 (1994-05-01), None
patent: 00264489 (1996-10-01), None
patent: WO-2004/097916 (2004-11-01), None
Kim Sun-joon
Seo Hyeoung-won
Pham Thanhha
Samsung Electronics Co,. Ltd.
Volentine & Whitt PLLC
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