Semiconductor die packaging tub having angularly offset pad-to-p

Details Semiconductor die packaging tub having angularly offset pad-to-p Semiconductor die packaging tub having angularly offset pad-to-p

1994-05-11

1996-12-17

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257686, 257723, 257777, H01L 2302, H01L 2334, H01L 2348

Patent

active

055856756

ABSTRACT:
A packaging assembly for a plurality of semiconductor circuit chips is comprised of a plurality of stacked tub-configured structures, each tub-configured structure including a floor portion sized to receive and mount thereon a respective semiconductor chip, and a surrounding wall portion having a top surface upon which a first arrangement of tub-to-tub bonding pads is formed and a bottom surface upon which a second arrangement of tub-to-tub bonding pads is formed. The first and second arrangements of tub-to-tub bonding pads are mutually aligned with one another along normals to the top and bottom surfaces of a tub, and an interconnect lead network connects a terminal pad of a respective chip with a respective bonding tub-to-tub bonding pad. Each tub-configured chip mounting architecture has an identically configured pad extension layer associated with the same prescribed bonding pad. Conductive pad-to-pad vias extend through the surrounding wall portion between respective ones of the first and second arrangements of tub-to-tub bonding pads at an angle offset from normals to the top and bottom surfaces of the tub. As a result, angularly offset via paths are provided through the stacked tub-configured structures.

REFERENCES:
patent: 4525921 (1985-07-01), Carson
patent: 4734825 (1988-03-01), Peterson
patent: 4862249 (1989-08-01), Carlson
patent: 5434452 (1995-07-01), Higgins, III

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