Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-01-17
2004-12-14
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C257S620000, C257S621000, C257S730000
Reexamination Certificate
active
06830959
ABSTRACT:
BACKGROUND OF THE INVENTION
There are a number of semiconductor die packages. In one example of a semiconductor die package, a semiconductor die is mounted to a lead frame with leads. Wires couple the semiconductor die to the leads. The wires, the semiconductor die and then the most of the lead frame (except for the leads that extend outward) are then encapsulated in a molding material. The molding material is then shaped. The formed semiconductor die package includes a molded body that has leads extending laterally away from the molded body. The semiconductor die package is then mounted onto a circuit board.
While such semiconductor die packages are useful, improvements could be made. For example, as consumer electronics (e.g., cell phones, laptop computers, etc.) continue to decrease in size, there is an increasing demand to decrease the thickness of electronic devices while increasing the density of devices. In addition, there is a need to improve the heat dissipation properties of a conventional semiconductor die package. Dissipating heat from chips is a continuing problem in the field of semiconductor packaging. Other problems that need to be addressed include reducing the “on resistance” (RDSon) of components on a circuit board and reducing the footprint of components on a circuit board. With respect to the footprint of such components, in the above molded package example, the leads that extend laterally away from the molded body increase the footprint of the package. It would be desirable if the footprint of such components could be reduced so that more components could be placed on a circuit board. For example, for a semiconductor die including a power MOSFET including a source region, a gate region, and a drain region, it would be desirable to ultimately achieve about a 1:1 chip to package size ratio without reducing the effective source area in the semiconductor die.
Embodiments of the invention address these and other problems individually and collectively.
SUMMARY OF THE INVENTION
Embodiments of the invention relate to semiconductor die packages.
One embodiment of the invention is directed to a method comprising: (a) forming a semiconductor wafer comprising a plurality of semiconductor dies defined by scribe lines; (b) forming a plurality of cavities in the semiconductor wafer in the vicinity of the scribe lines; and (c) dicing the wafer along the scribe lines to separate the semiconductor dies, wherein each separated semiconductor die comprises a vertical transistor and includes at least one recess at an edge of the semiconductor die.
Another embodiment of the invention is directed to a semiconductor die package comprising: (a) a circuit substrate including a conductive region; (b) a semiconductor die on the circuit substrate, wherein the semiconductor die comprises a vertical transistor and includes an edge and a recess at the edge; and (c) a solder joint coupling the semiconductor die and the conductive region through the recess.
These and other embodiments of the invention are described in further detail below.
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Fairchild Semiconductor Corporation
Ha Nathan W.
Pham Long
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