Semiconductor die package including exposed connections

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

Reexamination Certificate

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C438S107000, C438S123000, C438S117000, C257S706000, C257SE21514, C257SE21510, C257SE23046

Reexamination Certificate

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07972906

ABSTRACT:
A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.

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patent: 2007/0155058 (2007-07-01), Jereza
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patent: 2008/0054417 (2008-03-01), Lee et al.
patent: 2008/0173991 (2008-07-01), Cruz et al.
“Polarpak Product Information,” [Online] 2007, [Retrieved on Feb. 18, 2009], Retrieved from: http://www.vishay.com/product?docid=73199&query=sie800df. Entire document.

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