Semiconductor die manufacture method to limit a voltage drop...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C257S528000, C257S666000, C257S707000, C257S712000, C257S724000

Reexamination Certificate

active

06519744

ABSTRACT:

BACKGROUND OF THE INVENTION
1). Field of the Invention
This invention relates to a method of manufacturing a semiconductor die to limit a voltage drop on a power plane thereof.
2). Discussion of Related Art
Integrated circuits are often manufactured on semiconductor substrates and may include many (literally millions) transistors, capacitors, diodes and other electrical elements. The integrated circuit also includes a power plane (Vcc plane) and a ground plane (Vss plane). Many of the electrical elements are connected to the Vcc plane and other ones of the electrical components are connected to other electrical components which are connected to the power plane.
A voltage of a predetermined magnitude is applied to the power plane. It is required that a voltage level at respective points on the power plane to which the electrical elements are connected be sufficiently close to the voltage applied to the power plane in order to ensure correct functioning of the elements of the integrated circuit. The integrated circuit should therefore be designed in a manner wherein there is not an unreasonably high voltage drop on the power plane.


REFERENCES:
patent: 4695794 (1987-09-01), Bargett et al.
patent: 5713666 (1998-02-01), Seelin et al.
patent: 6168311 (2001-01-01), Xiao et al.
patent: 6311782 (2001-12-01), White et al.

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