Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-06-15
2004-01-27
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S691000, C257S692000, C257S693000, C257S698000, C257S730000
Reexamination Certificate
active
06683375
ABSTRACT:
BACKGROUND OF THE INVENTION
There are many different levels of packages and interconnections in state-of-the-art electronic packages. In a typical first level packaging process, a silicon die is joined to a ceramic substrate carrier. In a typical second level packaging process, the ceramic substrate carrier with the die is mounted on an organic board.
In one conventional method for forming a first level package, a passivation layer is formed on a semiconductor die (which may be in a semiconductor wafer). The passivation layer includes apertures that expose metal regions on the semiconductor die. Titanium and copper layers are sputtered on the upper surface of the conductive regions and the passivation layer. A layer of photoresist is then patterned on the semiconductor die so that the apertures in the patterned photoresist layer are over the conductive regions. Solder is electroplated in the apertures in the photoresist layer until the apertures are filled with solder. The photoresist is stripped and the portions of the titanium and copper layers around the solder deposits are removed. Then, the solder deposits are subjected to a full reflow process. The full reflow process causes the solder deposits to form solder balls. After forming the solder balls, the semiconductor die is bonded face-down to a carrier. The solder balls on the semiconductor die contact conductive regions on the chip carrier. Non-soluble barriers are disposed around the conductive regions and constrain the solder balls. The solder balls between the conductive regions on the carrier and the semiconductor die melt and wet the conductive regions on the carrier. Surface tension prevents the melting solder from completely collapsing and holds the semiconductor die suspended above the carrier.
While such conventional methods are effective in some instances, a number of improvements could be made. For example, during the reflow step, the deposited solder substantially deforms into solder balls. Because of the deformation, the heights of the resulting solder balls on the semiconductor die can be uneven. If the heights of the solder balls are uneven, the solder balls may not all contact the conductive regions of the carrier simultaneously when the semiconductor die is mounted to the chip carrier. If this happens, the strength of the formed solder joints may be weak thus potentially decreasing the reliability of the formed package. Also, the area of contact between the conductive regions and the solder balls are small, because the areas at the tips of the solder balls are small. It would be desirable to increase the area of contact between the solder and the carrier so that better conduction between the semiconductor die and the carrier occurs. Moreover, during the reflow process, the deposited solder is exposed to high temperatures for extended periods of time. Excessively heating the deposited solder can promote excessive intermetallic growth in the solder deposits. Intermetallics in the solder joints make the solder joints brittle and reduce the fatigue resistance of the solder joints. Lastly, performing a full reflow process takes time and energy and thus adds to the cost of the die package that is finally produced. If possible, it would be desirable to reduce the time and energy associated with the full reflow process.
Embodiments of the invention address these and other problems.
SUMMARY OF THE INVENTION
Embodiments of the invention include semiconductor die packages and methods for forming semiconductor die packages.
One embodiment of the invention is directed to a method for forming a semiconductor die package, the method comprising: a) providing a mask having an aperture on a semiconductor substrate, wherein a conductive region is on the semiconductor substrate and the aperture in the mask is disposed over the conductive region; b) placing a pre-formed conductive column within the aperture; and c) bonding the pre-formed conductive column to the conductive region, wherein the pre-formed conductive column has substantially the same shape before and after bonding.
A method for forming a semiconductor die package, the method comprising: a) forming a passivation layer comprising a first aperture on a semiconductor substrate comprising a conductive region, wherein the aperture in the mask is disposed over the conductive region; b) forming an adhesion layer on the passivation layer and on the conductive region; c) forming a seed layer on the adhesion layer; d) forming a patterned photoresist layer comprising a second aperture on the passivation layer, wherein the second aperture is over the conductive region and is aligned with the first aperture; e) electroplating a conductive layer within the second aperture and on the seed layer; f) depositing solder paste containing a flux within the second aperture and on the electroplated conductive layer; g) inserting a pre-formed conductive column into the second aperture; h) placing the pre-formed conductive column on the conductive layer within the second aperture; i) removing the patterned photoresist layer; j) etching portions of the adhesion layer and the seed layer disposed around the bonded pre-formed conductive column; and k) heating the solder paste to bond the pre-formed conductive column to the conductive region on the semiconductor substrate.
Another embodiment of the invention is directed to a method for forming a semiconductor die package, the method comprising: a) forming a mask comprising an aperture disposed over a conductive region on a semiconductor substrate, wherein the aperture is disposed over the conductive region; b) plating a conductive column within the second aperture and on the conductive region; and c) removing the mask from the semiconductor substrate.
Another embodiment of the invention is directed to a semiconductor die package comprising: a) a semiconductor die; b) a conductive region on the semiconductor substrate; c) a passivation layer comprising an aperture on the semiconductor substrate, wherein the aperture is disposed over the conductive region; and d) a pre-formed, conductive column comprising a lead-free, conductive columnar body and a coating on a conductive columnar body.
These and other embodiments of the invention are described in further detail below.
REFERENCES:
patent: 3401126 (1968-09-01), Miller et al.
patent: 3429040 (1969-02-01), Miller
patent: 4545610 (1985-10-01), Lakritz et al.
patent: 4980753 (1990-12-01), Dunaway et al.
patent: 5092036 (1992-03-01), Hu et al.
patent: 5284796 (1994-02-01), Nakanishi et al.
patent: 5288944 (1994-02-01), Bronson et al.
patent: 5346857 (1994-09-01), Scharr et al.
patent: 5355283 (1994-10-01), Marrs et al.
patent: 5359768 (1994-11-01), Haley
patent: 5515604 (1996-05-01), Horine et al.
patent: 5536362 (1996-07-01), Love et al.
patent: 5567657 (1996-10-01), Wojnarowski et al.
patent: 5636104 (1997-06-01), Oh
patent: 5639696 (1997-06-01), Liang et al.
patent: 5641990 (1997-06-01), Chiu
patent: 5678287 (1997-10-01), Smith et al.
patent: 5710062 (1998-01-01), Sawai et al.
patent: 5847929 (1998-12-01), Bernier et al.
patent: 6013571 (2000-01-01), Morrell
patent: 6060769 (2000-05-01), Wark
patent: 6133634 (2000-10-01), Joshi
patent: 6201679 (2001-03-01), Richiuso
patent: 6251707 (2001-06-01), Bernier et al.
patent: 6294406 (2001-09-01), Bertin et al.
patent: 6307755 (2001-10-01), Williams et al.
patent: 6339191 (2002-01-01), Crane, Jr. et al.
patent: 6346469 (2002-02-01), Greer
patent: 6372553 (2002-04-01), Briar
patent: 6391687 (2002-05-01), Cabahug et al.
patent: 6429533 (2002-08-01), Li et al.
patent: 2002/0005591 (2002-01-01), Lin
patent: 2002/0070842 (2002-06-01), Heaney
patent: 2002/0100973 (2002-08-01), Akram et al.
patent: 309651 (1997-10-01), None
Joshi Rajeev
Wu Chung-Lin
Fairchild Semiconductor Corporation
Soward Ida M.
Townsend and Townsend / and Crew LLP
Zarabian Amir
LandOfFree
Semiconductor die including conductive columns does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor die including conductive columns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor die including conductive columns will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3201807