Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Patent
1997-03-12
2000-02-08
Picardat, Kevin M.
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
438612, 438618, H01L 21301
Patent
active
060227923
ABSTRACT:
To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
REFERENCES:
patent: 4073055 (1978-02-01), Kimura et al.
patent: 5451549 (1995-09-01), Oki et al.
patent: 5542174 (1996-08-01), Chiu
patent: 5840593 (1998-11-01), Leedy
Akiba Takao
Inoue Naoto
Ishii Kazutoshi
Kadoi Kiyoaki
Kojima Yoshikazu
Picardat Kevin M.
Seiko Instruments Inc.
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