Semiconductor devices with scalable two transistor memory cells

Details Semiconductor devices with scalable two transistor memory cells Semiconductor devices with scalable two transistor memory cells

2005-06-07

2005-06-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S321000

Reexamination Certificate

active

06903409

ABSTRACT:
Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

REFERENCES:
patent: 5427966 (1995-06-01), Komori et al.
patent: 5952692 (1999-09-01), Nakazato et al.

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