Semiconductor devices with multiple isolation structure and...

Details Semiconductor devices with multiple isolation structure and... Semiconductor devices with multiple isolation structure and...

2003-02-25

2004-11-09

Lake, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including high voltage or high power devices isolated from...

C257S329000, C257S335000, C257S287000, C257S343000, C257S341000, C438S207000, C438S355000, C438S262000, C438S268000, C438S258000

Reexamination Certificate

active

06815794

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2002-11621, filed on Mar. 5, 2002, which is fully incorporated herein by reference.
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for fabricating the same. More specifically, the present invention relates to semiconductor devices with multiple isolation structure and methods for fabricating the same.
BACKGROUND
Currently, the use of power IC (integrated circuit) products has been expanding to various applications including, e.g., power conversion systems and power control systems and other applications that require large power transmission capacity and high-speed switching. In particular, power IC products are widely used for hard disk drive (HDD), video tape recorder (VTR), and car electronics IC. Double diffused MOS (DMOS) transistors are typically used in power IC products for processing high voltages because such components are highly capable of processing large currents per unit region and have low on-resistance. Since DMOS devices operate at high voltages, device isolation structures with high breakdown voltages are needed between DMOS devices and between a DMOS device and other control circuits. Conventionally, a junction isolation technique using an impurity diffused layer is typically used for device isolation. With this technique, however, a large area is needed for forming a deep device isolation structure. To overcome this problem, various methods for using trench isolation structures have been recently proposed. For example, a method for isolating devices by forming a DMOS device on a silicon on insulator (SOI) substrate is described in U.S. Pat. No. 5,356,822, entitled “
Method For Making All Complementary DiCDMOS Devices”.
FIG. 1
is a cross-sectional view of a conventional DMOS device having a device isolation structure that is formed using a conventional junction isolation technique. In
FIG. 1
, a DMOS device comprises a buried layer
6
(having a first conductivity type) which is disposed in a predetermined region of a semiconductor substrate
1
, and a buried layer
2
(having a second conductivity type) which is separated from the buried layer
6
by a predetermined space and which surrounds the buried layer
6
. An epitaxial layer
8
(having a first conductivity type) is formed on the entire surface of the semiconductor substrate
1
including the buried layers
6
and
2
. The epitaxial layer
8
has the same conductivity type of the buried layer but is doped to a lower concentration than the buried layer
6
. A junction isolation layer
4
(having a second conductivity type) surrounds a predetermined region of the epitaxial layer
8
and penetrates the epitaxial layer
8
to connect to the buried layer
2
. The junction isolation layer
4
and the buried layer
2
form a device isolation structure
5
of the DMOS device. The device isolation structure
5
defines a device region of the DMOS device.
A field oxide layer
16
is disposed on a predetermined region of the device region surrounded by the device isolation structure
5
, thereby defining first and second active regions. The field oxide layer
16
is separated from the device isolation structure
5
to surround the first active region. A gate electrode
14
is disposed on the first active region and a gate insulation layer
22
is formed between the first active region and the gate electrode
14
.
A source region is disposed in the first active region adjacent to the gate electrode
14
, and a drain region is disposed in the second active region. The source region comprises a diffused region
18
of first conductivity type formed in a surface of the first active region adjacent to the gate electrode
14
, a diffused region
20
of second conductivity type separated from the gate electrode
14
adjacent to the diffused layer
18
of first conductivity type, and a body region
26
of second conductivity type surrounding the diffused regions
14
and
20
of first and second conductivity types. The drain region comprises a sink region
10
that vertically penetrates the epitaxial layer
8
to connect to the buried layer
6
of first conductivity type, and a heavily doped region
12
formed in a surface of the second active region of an upper portion of the sink region
10
.
Conventionally, the breakdown voltage of the DMOS device is proportional to a thickness of the epitaxial layer
8
. More particularly, to form the DMOS device with a high breakdown voltage, the epitaxial layer
8
should be formed to a thickness of 10 &mgr;m. Accordingly, when the junction isolation layer
4
is formed to penetrate the thick epitaxial layer
8
, a sufficient space is required between the junction isolation layer
4
and the drain region in consideration for diffusion of impurities contained in the junction isolation layer
4
of second conductivity type. As a result, in a DMOS device where the junction isolation technique is applied, an area occupied by the device isolation structure is equivalent to more than 25% of an entire area of the DMOS device.
FIG. 2
is a diagram of a DMOS device having a trench isolation structure, which has been proposed to overcome problems associated with the junction isolation technique. The DMOS device comprises a buried layer
36
(having a first conductivity type) formed in a semiconductor substrate
31
, an epitaxial layer
38
that covers an entire surface of the semiconductor substrate
31
, a gate electrode
34
, a source region and a drain region. The source and drain regions have the same structure as the source and drain regions of the a DMOS device of FIG.
1
. In particular, the source region includes a diffused layer
48
of first conductivity type, a diffused layer
30
of second conductivity type, and a body region
44
of second conductivity type. The drain region includes a sink region
40
connected to the buried layer
36
and a heavily doped region
42
formed in an upper portion of the sink region
40
.
A device isolation structure
32
is formed to penetrate the epitaxial layer
38
and a portion of the semiconductor substrate
31
. The device isolation structure
32
defines a device region. A field oxide layer
46
is disposed on a predetermined region of the device region surrounded by the device isolation structure
32
, thereby defining first and second active regions. The gate electrode
34
and the source region are disposed on the first active region surrounded by the field oxide layer
46
. The drain region is disposed in the second active region between the field oxide layer
46
and the device isolation structure
32
.
As illustrated in
FIG. 2
, the device isolation structure
32
is preferably formed deeper than the buried layer
36
to isolate adjacent DMOS devices from each other and other control circuits. For example, in a DMOS device with an operating voltage of about 70V, the device isolation structure
32
is preferably formed to have a depth of about 20 &mgr;m or more. However, it is difficult to form a deep trench isolation structure in a narrow area using conventional methods due to drawbacks of etching and burying processes.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device that provides a high operating voltage, and a method for fabricating the same. A semiconductor device according to the invention comprises a device isolation structure which exhibits reliable device isolation characteristics and which occupies less area than that of a device region.
According to one aspect of the invention, a semiconductor device having a multiple isolation structure, comprises a heavily doped buried layer of a first conductivity type and an epitaxial layer covering an entire surface of the semiconductor substrate including the buried layer. A device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. A field oxide layer is disposed on the device region, thereby defining first and second active regions.

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