Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2002-07-17
2004-09-14
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S786000, C438S612000
Reexamination Certificate
active
06791196
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 2001-0075867, filed on Dec. 3, 2001 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of bonding pads of semiconductor devices, and more specifically to semiconductor devices with bonding pads that have an intermetal dielectric layer of hybrid configuration, and methods of fabricating the same.
2. Description of the Related Art
Semiconductor devices include circuits. The circuits terminate in bonding pads, and are accessed through the bonding pads.
Referring now to
FIG. 1A
, a top surface of a bonding pad
100
in the prior art is shown. The bonding pad is accessed from the top surface. A dashed line
104
denotes a recess.
Referring now to
FIG. 1B
, a sectional view of pad
100
is shown. It is made with two conductive layers
114
,
120
, on a substrate
110
. Layer
120
is typically made of aluminum, while layer
114
may be made from either aluminum or polycrystalline silicon.
FIG. 1B
also shows the intended uses of bonding pad
100
. First, after a device is initially fabricated, it is tested before packaging. Testing is called electrical die sorting (EDS), and is performed by moving an electrical lead
140
according to an arrow
142
. Lead
140
is brought temporarily to contact the top surface of layer
120
. Voltages are then applied and/or received through lead
140
for testing. After testing, lead
140
is withdrawn.
If the circuit is deemed acceptable after testing, then it is packaged. Prior to packaging, a bump
160
is deposited on, and attached to the top surface of layer
120
. When the device will be in operation, then voltages are applied and/or received through bump
160
. Alternately, instead of bump
160
, a soldering wire (not shown) may be attached to the top surface of layer
120
.
The device of
FIG. 1B
has problems. First, during fabrication, layer
120
may be subjected to a Chemical Mechanical Polishing (CMP) process. This can cause a dishing phenomenon, where a center portion may be polished away, thus exposing and subjecting layer
114
to damage. Second, when lead
140
is pressed upon bonding pad
100
, it tends to scratch at least the top surface of layer
120
.
Referring now to
FIG. 2A
, later bonding pads are described. In between layers
114
,
120
, there is an intermediate layer of rapidly alternating thin portions of inter-metal dielectric (IMD)
116
and tungsten (W)
118
along an intermediate plane
250
. The portions of contacts
118
establish the electrical connection between lower conducting layer
114
and upper conducting layer
120
. Two possible patterns of IMD
116
and W
118
in intermediate plane
250
are described below.
Referring to
FIG. 2B
, a pattern
250
-A of IMD
116
and W
118
is contact-type. A grid of inter-metal dielectric
116
is fully permeated with openings, from which W contacts
118
emerge. In this case, W contacts
118
are also called W plugs
118
.
Referring to
FIG. 2C
, a pattern
250
-B of MD
116
and W
118
is mesh-type. A mesh of W
118
is fully permeated with openings, in which there are islands of inter-metal dielectric
116
.
In the patterns
250
-A and
250
-B, the portions of dielectric
116
and W
118
are alternating rapidly throughout the intermediate layer, if considered along section lines. A relevant characteristic is that tungsten (W) is used in the intermediate layer, instead of aluminum. The reason is that the openings for it are very narrow, and becoming further narrower as integration of devices increases. Since the openings are narrow, using an aluminum flowing process to deposit aluminum could leave one or more voids in some of the openings. These voids would contribute to parasitic electrical resistance, which is why tungsten is preferred to aluminum.
In preparing a device according to
FIG. 2A
,
FIG. 2B
,
FIG. 2C
, a CMP process can be performed to remove any excess tungsten (W) that protrudes above the portions of intermetal dielectric
116
. The portions of inter-metal dielectric
116
act as a stop to the CMP process. Their dense formation prevents any dishing phenomenon.
Bonding pad
200
has problems, some of which develop from the way that bonding pad
200
is tested and then packaged. These are discussed below.
Referring now to
FIG. 3A
, bonding pad
200
is shown being tested by lead
140
. A hazard is that lead
140
may scratch off pieces of layer
120
.
Referring now to
FIG. 3B
, a photograph of a top view of bonding pad
200
is shown, after being scratched as in FIG.
3
A. Scratching exposes the IMD portions
116
, which is undesirable.
Referring now to
FIG. 3C
, scratched bonding pad
200
is shown with a bump
260
being deposited and attached. Portions of a passivation layer
122
are also shown, which further guide where bump
260
would be located.
A problem in the scratched bonding pad of
FIG. 3C
is that bump
260
contacts layer
114
also through IMD portions
116
. These provide weak adhesion of bump
260
to pad
200
.
Referring now to
FIG. 3D
, due to the weak adhesion, bump
260
may be peeled off (lifted) entirely from bonding pad
200
. In some instances, it may leave a residue
262
.
In other words, if second metal pad
120
is damaged due to the probe pin, the intermetal dielectric (IMD) layer
116
as well as the tungsten plug
118
may be exposed. Since the IMD layer
116
is composed of oxide material, and oxide has poor adhesive force with a metal layer, bump
260
is frequently lifted due to the weak adhesion between the exposed IMD layer
116
and bump
260
.
Referring now to
FIG. 3E
, a photograph of a top view of bonding pad
200
is shown, after bump
260
has been lifted as in FIG.
3
D. Once the bump has been thus dislodged, the manufacturing yield is reduced.
Referring now to
FIG. 4
, another device
400
in the prior art is described, which is first taught in U.S. Pat. No. 6,034,439. The reference numerals have been adapted to match substantially corresponding numerals of the previous discussion. Layer
114
is made from polysilicon.
Device
400
comprises a first conductor
114
such as polysilicon layer, a large contact hole, and a plurality of small contact holes. The small contact holes are located around the large contact hole, metal spacers on the sidewalls of the large contact hole and the small contact holes, and a second conductor, such as aluminum.
Thus, aluminum pad
120
contacts directly polysilicon pad
114
through the large contact hole and the small contact holes. At this point, particles can be generated due to the tungsten spacer during the wet cleaning process applied prior to the formation of the aluminum pad. Therefore the yield of the device decreases due to the particles.
BRIEF SUMMARY OF THE INVENTION
The present invention overcomes these problems and limitations of the prior art.
Generally, the present invention provides devices that have bonding pads, and methods for fabricating the same. The bonding pads have two conductive layers, and an intermediate layer between them. The intermediate layer has a hybrid configuration of a relatively large conductive plate section, and a mixed plugs/mesh section. The plugs/mesh section has conductive portions interspersed with non-conducting portions, with features that are relatively small in size.
The hybrid configuration of the intermediate layer of the invention achieves a proper balance between the plate section for the main electrical contact, and the plugs/mesh section for support and additional current density. Indeed, the plate section is substantially larger than the average size of features in the plugs/mesh section. The plate is small enough to limit a dishing phenomenon in fabricating the plate section.
Even if a top layer is scratched, neither the non-conducting IMD layer, nor the lower layer are exposed. Only the metal plate will be exposed. And since it is metal, adhesion of the bump
Kang Sa Yoon
Kwon Dong Whee
Lee Jin Hyuk
Song Yun Heub
Clark Sheila V.
Marger & Johnson & McCollom, P.C.
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