Semiconductor devices including stress inducing layers

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S349000, C257S368000, C257SE29113

Reexamination Certificate

active

11190254

ABSTRACT:
A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

REFERENCES:
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patent: 6380558 (2002-04-01), Yamazaki et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
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patent: 7005330 (2006-02-01), Yeo et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2005/0224889 (2005-10-01), Oh et al.
T. Ghani et al;A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors, Proceedings of the 2003 International Election Devices Meeting.
T. Ghani et al;A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors, Proceedings of the 2003 International Election Devices Meeting (SLIDES).
Korean Office Action for Korean Patent Application No. 10-2004-0058785 mailed on Feb. 28, 2006.

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