Semiconductor devices including a silicon-on-insulator layer

Details Semiconductor devices including a silicon-on-insulator layer Semiconductor devices including a silicon-on-insulator layer

2001-12-19

2004-09-07

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000

Reexamination Certificate

active

06787851

ABSTRACT:

Applicant hereby incorporates by reference Japanese Application No. 2000-385530, filed Dec. 19, 2000, in its entirety.
1. Technical Field
The present invention relates to semiconductor devices and may include semiconductor devices that are applied to a CMOS inverter circuit using a partially depleted SOI—CMOSFET with a floating body.
2. Related Art
A conventional semiconductor device is described below.
A CMOS inverter circuit using a partially depleted SOI (silicon on insulator)—CMOSFET in certain forms may be considered as a conventional semiconductor device. However, this CMOS inverter circuit in conventional form has a problem of duty cycle dependency of input signals which results from substrate floating effects, which is observed as an inverter delay time.
The following three semiconductor devices can be considered as means which may solve the above described problem.
As a first semiconductor device, a fully depleted SOI—MOSFET that does not show the substrate floating effect may be used. Also, as a second semiconductor device, a semiconductor device, in which a body is provided with a terminal and its potential is fixed at a source potential to restrict the substrate floating effect, in other word, a body-tied-to-source operation is conducted, may be used. Also, as a third semiconductor device, a semiconductor device, in which a body is provided with a terminal and its potential is fixed at a gate potential to restrict the substrate floating effect, in other word, a body-tied-to-gate operation is conducted, may be used.


REFERENCES:
patent: 5315144 (1994-05-01), Cherne
patent: 5410172 (1995-04-01), Koizumi et al.
patent: 5488243 (1996-01-01), Tsuruta et al.
patent: 5614433 (1997-03-01), Mandelman
patent: 5780899 (1998-07-01), Hu et al.
patent: 6060749 (2000-05-01), Wu
patent: 6096583 (2000-08-01), Iwamatsu et al.
patent: 6300172 (2001-10-01), Ang et al.
patent: 6339244 (2002-01-01), Krivokapic
patent: 6353245 (2002-03-01), Unnikrishnan
patent: 6358783 (2002-03-01), Yamaguchi et al.
patent: 2001/0029067 (2001-10-01), Hirano
patent: 2001/0045602 (2001-11-01), Maeda et al.
patent: 2002/0022366 (2002-02-01), Cabral et al.
Wei and Antoniadis, “Minimizing Floating-Body-Induced Threshold Voltage Variation in Partialy Depleted SOI CMOS,”IEEE Electron Devices Letters, vol. 17, No. 8 (Aug. 1996) at pp. 391-394.

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