Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-06-01
2003-11-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S728000, C714S729000, C714S730000
Reexamination Certificate
active
06647522
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a method for testing a semiconductor device that includes a plurality of memory circuits having different configurations.
Both logic circuits and mass storage memory circuits can be arranged on the same semiconductor device (LSI). Further, to perform multiple functions, the memory circuits on the LSI chip can have differing capacities and bus widths.
The logic circuits and memory circuits are tested with a tester before the LSI is shipped out of the factory. If a DRAM is arranged on the LSI chip, there may be a plurality of deficient modes due to the DRAM configuration. To eliminate such deficient modes, tests must be performed on the memory circuits under various conditions using a large number of data patterns. Thus, if the number of memory circuits on the LSI increases, the testing time becomes longer and the cost of the LSI chip increases.
FIG. 1
is a schematic block circuit diagram showing a prior art semiconductor device
11
provided with memory circuits
12
,
13
. The memory circuits
12
,
13
have different configurations and are designed in accordance with a RAM-SCAN mode.
The memory circuit
12
includes a memory section
14
and a scan chain
15
. The scan chain
15
incorporates scan type flip flops (hereafter referred to as SFF)
16
, the number of which corresponds to the number of input/output bits of the memory section
14
. The SFFs
16
are connected in a daisy chain. The scan chain
15
receives a test signal TI via a scan data input terminal SDI in synchronism with a scan clock (not shown) of the SFFs
16
. Then, the scan chain
15
functions as a shift register and outputs a shifted test signal from a scan data output terminal SDO. The scan data output terminal SDO is connected to another scan chain
17
located outside the memory circuit
12
. The scan chain
17
has SFFs
16
connected in series with the SFFs
16
of the scan chain
15
.
The memory circuit
13
includes a memory section
18
and a scan chain
19
. The scan chain
19
incorporates SFFs
16
, the number of which corresponds with the number of input/output bits of the memory section
18
. Each of the SFFs
16
are connected in a daisy chain. The scan chain
19
functions as a shift register in accordance with a scan clock (not shown). An output terminal of the memory circuit
13
is connected to another scan chain
20
, which includes SFFs
16
connected in series with the SFFs
16
of the scan chain
19
.
When a test mode is entered, a tester (not shown) connected to an external terminal
21
provides a serial test signal TI to the memory circuits
12
,
13
. The scan chains
15
,
19
shift the test signal TI and provide the shifted test signal TI to the respective memory sections
14
,
18
as addresses and input data. The scan chains
17
,
20
provide the output data from the associated memory circuits
12
,
13
to a selection circuit
22
as serial test output data.
The selection circuit
22
selects the test output data of the memory circuit
12
or the test output data of the memory circuit
13
in accordance with a memory select signal MS
0
provided from the tester via an external terminal
23
. Then, the selection circuit
22
provides the selected test output data to the tester via an external terminal
24
. The tester determines whether or not the memory circuit
12
,
13
is defective based on the test output data.
However, since the test pattern data of the memory circuits
12
,
13
differs in accordance with their size and data lengths, the tester must test the memory circuits
12
,
13
separately. For example, if the memory circuits
12
,
13
are both tested using the test pattern data of the memory circuit
12
, pattern data differing from the desired pattern is stored in the memory section
18
of the memory circuit
13
. Hence, the test result related to the memory circuit
13
, which is based on the output data from the memory section
18
, is erroneous.
Further, since the test pattern data, which is complicated and used to identify a large number of deficient modes, differs between each memory circuit in accordance with the memory circuit's capacity, the amount of the test pattern data is relatively large. Accordingly, the generation of test patterns for all of the memory circuits takes a long time. This increases the total time required for memory circuit testing (preparation time and actual testing time) and, consequently, the cost of the LSI chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that requires less time to test a plurality of memory circuits.
To achieve the above object, the present invention provides a semiconductor device having a plurality of memory circuits including a first memory circuit and a second memory circuit. The first memory circuit includes a first memory having a first address width and a first data width, a first address scan chain connected to the first memory to receive serial scan-in addresses and generate a first address signal corresponding to the first address width, and a first data scan chain connected to the first memory to receive serial scan-in data and generate a first data input signal corresponding to the first data width. The second memory circuit includes a second memory having a second address width differing from the first address width and a second data width differing from the first data width, a second address scan chain connected to the second memory to receive the serial scan-in addresses and generate a second address signal corresponding to the second address width, and a second data scan chain connected to the second memory to receive the serial scan-in data and generate a second data input signal corresponding to the second data width.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
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Hiramatsu Tetsuya
Kato Kiminori
Kawakami Yasuhiro
Nakahara Hideaki
Sudo Masahiko
De'cady Albert
Fujitsu Limited
Staas & Halsey , LLP
Torres Joseph D.
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