Semiconductor devices having multi-level metal interconnects

Details Semiconductor devices having multi-level metal interconnects Semiconductor devices having multi-level metal interconnects

1988-04-08

1989-05-23

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156653, 156656, 156657, 1566591, 357 71, 437203, 437228, B44C 122, C23F 102, C03C 1500, C03C 2506

Patent

active

048327891

ABSTRACT:
A self-assigned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric and then, using an etch stop layer on top of the dielectric to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate are etched in the dielectric. Self-aligned windows can also be formed without a mask.

REFERENCES:
patent: 4370405 (1983-01-01), O'Toole et al.
patent: 4605470 (1986-08-01), Gwozdz et al.
patent: 4631806 (1986-12-01), Poppert et al.
A Planar Multi-Level Tungsten Interconnect Technology, D. C. Thomas and S. S. Wong, IEDM Technical Digest, pp. 811-813, Los Angeles, CA 1986.
Prairie-A New Planarization Technique and its Applications in VLSI Multilevel Interconnection, Andy L. Wu, Electrochemical Society Proceedings, 87-4, pp. 239-249, 1987.

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