Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-11-03
2009-06-09
Monbleau, Davienne (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000, C257SE21507, C257SE23019
Reexamination Certificate
active
07545046
ABSTRACT:
A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed two conducting line patterns on a semiconductor substrate. Each of the conducting line patterns includes a conducting line and a conducting line capping layer pattern stacked thereon. Each of the conducting line patterns has a trench between the conducting line capping layer pattern and the conducting line. Conducting line spacers are formed between the conducting line patterns. One conducting line spacer covers a portion of a sidewall of one of the conducting line patterns, and the remaining conducting line spacer covers an entire sidewall of the remaining conducting line pattern. A landing pad is disposed between the conducting line patterns.
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patent: 6117733 (2000-09-01), Sung et al.
patent: 6335237 (2002-01-01), Tang et al.
patent: 2002/0175381 (2002-11-01), Choi et al.
patent: 2004-0017982 (2004-03-01), None
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English language abstract of Korean Publication No. 1998-5566.
English language abstract of Korean Publication No. 1999-0061078.
English language abstract of Korean Publication No. 2004-14065.
Ahn Chang-Moon
Choi Joong-Sup
Kang Wi-Seob
Lee Seung-Kun
Nam Chang-Hyeon
Harrison Monica D
Marger & Johnson & McCollom, P.C.
Monbleau Davienne
Samsung Electronics Co,. Ltd.
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