Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-18
2004-02-17
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S577000
Reexamination Certificate
active
06693329
ABSTRACT:
Applicant hereby incorporates by reference Japanese Application No. 2001-011858, filed Jan. 19, 2001, in its entirety. Applicant hereby incorporates by reference U.S. patent application Ser. No. 10/050,793, filed on Jan. 18, 2002, in its entirety.
TECHNICAL FIELD
The present invention includes semiconductor devices having a field effect transistor and a bi-polar transistor, and methods for manufacturing the same.
RELATED ART
A MOS field effect transistor with an SOI (Silicon-on-Insulator) structure can be driven at a low power consumption and at a higher speed compared to an ordinary MOS field effect transistor.
FIG. 16
schematically shows one example of a MOS field effect transistor with an SOI structure. An embedded oxide film
1100
that is formed from a silicon oxide film is formed on a silicon substrate
2000
. A source region
1200
and a drain region
1300
are formed on the embedded oxide film
1100
. A body region
1400
is formed on the embedded oxide film
1100
and between the source region
1200
and the drain region
1300
. A gate electrode
1500
is formed over the body region
1400
through a gate dielectric layer.
It is noted that the body region
1400
of the MOS field effect transistor is in a floating state. Accordingly, carriers that are generated by an impact ionization phenomenon are stored in the body region
1400
. When carriers are stored in the body region
1400
, the potential of the body region
1400
changes. A phenomenon that is a so-called substrate floating effect takes place. When the substrate floating effect occurs, a kink phenomenon and a history effect occur in the MOS field effect transistor.
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patent: 5552624 (1996-09-01), Skotnicki et al.
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Parke et al., Bipolar-FET Hybrid-Mode Operation of Quarter-Micrometer SOI MOSFETs, May 1993, IEEE, Electron Device Letters, vol. 14, No. 5, pp. 234-236.*
U.S. Application Ser. No. 10/050,793, filed Jan. 18, 2002, having U.S. patent application Pub. No. US2002/0113266 A1, published Aug. 22, 2002.
U.S. Application Ser. No. 10/014,612, filed Dec. 14, 2001, having U.S. patent application Pub. No. US2002/0117721 A1, published Aug. 29, 2002.
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-011858 (from which priority is claimed in U.S. Ser. No. 10/050,792), which cites JP05/041488 and JP05-218316.
Wolf, Stanley,Silicon Processing for the VLSI Era; Lattice Press, 1990, vol. 2, pp. 557-558.
Zheng et al., “SOI bipolar-MOS merges transistors for BiCMOS appilcation”,Electronics Letters, vol. 35, Issue 14, Jul. 8, 1999 pp. 1203-1204.
Notice of Reasons of Rejection for Japanese Patent Application No. 2001-011859 (from which priority is claimed in U.S. patent application Ser. No. 10/050,793), and which cites JP05-041488 and JP05-218316, which were previously cited in an IDS.
Notice of Reasons of Rejection for Japanese Patent Application No. 2000-382395 (from which priority is claimed in U.S. patent application Ser. No. 10/014,612), and which cites JP05-041488 and JP05-218316, which were previously cited in an IDS.
Eckert George
Konrad Raynes & Victor & Mann LLP
Raynes Alan S.
Seiko Epson Corporation
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