Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1998-07-27
2001-01-02
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S321000, C257S410000
Utility Patent
active
06169306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to semiconductor devices, and, more particularly, to a structure for semiconductor devices and method for making same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to improve the performance of various semiconductor devices. Moreover, there is a constant drive to reduce the feature size, or scale, of the semiconductor devices. However, such scaling also leads to several problems. For example, as the thickness of traditional silicon dioxide gate dielectric layers is reduced, the ability of the silicon dioxide to perform its functions, e.g., prevent current leakage, may become impaired. Additionally, as such silicon dioxide gate dielectric layers are reduced in size, they become more difficult to manufacture with an acceptable level of quality and consistency.
For another example, many semiconductor devices employ a non-crystalline material, such as polysilicon, as part of the device, e.g., a polysilicon gate electrode for a field effect transistor, a polysilicon floating gate for a memory device, etc. However, given the non-crystalline or amorphous structure of these materials, the performance of various semiconductor devices may be impaired.
Such non-crystalline materials have a relatively large number of grain boundaries as compared to a material having a single crystal structure. As compared to crystalline material, the relatively large number of grain boundaries act to slow down the flow of electrons through, for example, the gate conductor of a field effect transistor. Also, use of such amorphous materials as, for example, a floating gate on a memory device, may reduce the ability of the floating gate to hold a charge. This is because there are fewer sites available within the non-crystalline material to hold electrons as compared to crystalline material.
There is also a constant drive in the semiconductor industry to reduce the number of process steps required to manufacture various types of semiconductor devices. Generally, the fewer process steps involved in manufacturing a semiconductor device, the lower the cost of manufacturing and the shorter the time required to manufacture the device. Additionally, it is desirable to reduce the number of times a given wafer, or lot of wafers, has to be moved from one piece of processing equipment to another piece of processing equipment. Reducing the number of times a wafer, or lot of wafers, is moved between processing equipment is desirable in that it will reduce the number of times the wafers are being handled by factory workers, reduce the number of opportunities for exposing the wafer to contaminants, and may reduce the time required to fabricate the completed semiconductor device, etc.
The present invention is directed to a semiconductor device that minimizes or reduces some or all of the aforementioned problems and a method for making same.
SUMMARY OF THE INVENTION
The present invention is directed to a novel semiconductor device. The device comprises a semiconducting substrate and a first layer of epitaxial metal oxide positioned above the substrate. The device further comprises a gate conductor positioned above the layer of epitaxial metal oxide and at least one source/drain region.
The present invention also includes a novel method of making semiconductor devices. The method comprises forming a layer of epitaxial metal oxide above a semiconducting substrate and forming a layer of conductive material above the layer of epitaxial metal oxide. The method further comprises removing portions of the layer of epitaxial metal oxide and the layer of conductive material and forming at least one source/drain region.
The method further comprises forming different types of semiconductor devices above a semiconducting substrate. In one embodiment, the method comprises forming a first layer of epitaxial metal oxide above a semiconducting substrate, forming a second layer of epitaxial conductive material above the first layer, forming a third layer of epitaxial metal oxide above the second layer, and forming a fourth layer of conductive material above the third layer. The method further comprises removing the third and fourth layers in at least some of a plurality of first regions of the wafer where a first type of semiconductor device is to be formed, removing portions of the first and second layers in said first regions of the wafer to define a portion of the first type of semiconductor devices, and removing portions of the first, second, third and fourth layers in at least some of a plurality of second regions of the wafer where a second type of semiconductor device is to be formed.
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Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Eckert II George C.
Saadat Mahshid
Williams Morgan & Amerson
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