Semiconductor devices, circuits and methods for...

Details Semiconductor devices, circuits and methods for... Semiconductor devices, circuits and methods for...

2002-02-11

2003-08-05

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

06603687

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. P2002-01251, filed on Jan. 9, 2002 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of semiconductor memory devices, and more specifically to circuits for controlling clock delays or phases for inputting and outputting data into and out of such memory devices.
2. Description of the Related Art
Semiconductor devices, especially memory devices are used to store data. Data bits are stored by being input (“written”) in one or more arrays of memory cells. Later they are output (“read out”) from the memory cells.
Data is written into and read out of memory cell arrays in groups of synchronized bits. Some times the data of such a group is said to form a byte.
Synchronizing these operations is accomplished by using a clock signal throughout the device. An input clock signal CLK is provided, and often an internal clock IntCLK is additionally generated from the input clock signal CLK.
As memory devices are required to become faster, the clock signals become commensurately shorter. This allows less room for error in synchronizing inputting and outputting the data of a group.
To address this diminished room for error, present attempts are directed towards reducing the jitter of the internal clock IntCLK. The jitter arises from a number of factors, including variations in temperature, voltage, and method of manufacture of the device. Reducing the jitter reduces the margin of error, which reduces errors.
Reducing the jitter must take place both for data outputting operations (reading out), and also for data inputting operations (writing). The prior art provides two circuits in each memory device, one for writing data and one for reading data. Examples of these circuits are described below, using
FIGS. 1-4
.
Referring now to
FIG. 1
, a portion of a device
100
in the prior art is described, having a Memory Cell Array (MCA)
102
for storing data. Device
100
receives an input clock signal CLK.
Device
100
has a circuit
114
for locking a delay of a clock signal, so as to output groups of data from MCA
102
in a synchronized fashion. Circuit
114
is also known as a Delay Lock Loop (DLL) circuit.
Circuit
114
includes a variable delay circuit
122
. Variable delay circuit
122
receives input clock signal CLK, and an adjustment signal ADJ
1
. Variable delay circuit
122
outputs a read signal PCLKR, which is a delayed version from input clock signal CLK. The delay is by a variable amount, which is controlled by adjustment signal ADJ
1
.
Circuit
114
also includes a phase detector
124
. Phase detector
124
receives input clock signal CLK and a feedback clock signal FCLK
1
. It will be recognized from the below that feedback clock signal FCLK
1
is generated from read signal PCLKR, after being subjected to some delays.
Phase detector
124
outputs the adjustment signal ADJ
1
. Adjustment signal ADJ
1
is such that the inputs of phase detector
124
are maintained in phase. In other words, the adjustment signal ADJ
1
is such that the phase of the feedback clock signal FCLK
1
is maintained to coincide with the phase of the input clock signal CLK.
Read signal PCLKR is output into a Data Out (DOUT) clock tree
132
of device
100
. From there it is used to synchronize a group of DOUT Buffers
134
, as they receive output data DATA_OUT from Memory Cell Array (MCA)
102
. The output data is then forwarded to a group of DOUT Drivers
136
, and from there to a group of DOUT pads
138
.
Device
100
usually has a plurality of DOUT Pads, one for each of the data bits of the group. Examples include X
4
, X
8
, X
16
, X
32
, X
64
.
FIG. 1
shows the case of eight data bits (X
8
). Accordingly, group of DOUT Pads
138
includes individual DOUT pads
138
-
1
,
138
-
2
, . . . ,
138
-
8
. This additionally means that group of DOUT Buffers
134
is made from
8
individual buffers
134
-
1
,
134
-
2
, . . . ,
134
-
8
. Moreover, group of DOUT Drivers
136
is made from
8
individual buffers
136
-
1
,
136
-
2
, . . . ,
136
-
8
.
It will be appreciated that each of DOUT clock tree
132
, group of DOUT Buffers
134
, and group of DOUT Drivers
136
contributes a delay. These delays, along with their cumulative effect, may result in not synchronizing the outputting of data.
Returning to circuit
114
, a feedback loop is further made, which starts from variable delay circuit
122
and ends in phase detector
124
. The feedback loop receives internal clock signal PCLKR, and outputs feedback clock signal FCLK
1
.
The feedback loop is intended to replicate the delays along the path of DOUT clock tree
132
, group of DOUT Buffers
134
, and group of DOUT Drivers
136
. Accordingly, in the embodiment of
FIG. 1
, three delay elements
142
,
144
,
146
are provided, which may be made as replicas. In particular, delay element
142
may be made as a Replica DOUT Clock Tree
142
, delay element
144
may be made as a Replica DOUT Buffer
144
, and delay element
146
may be made as a Replica DOUT Driver
146
.
Referring now to
FIG. 2
, a timing diagram is shown to describe the operation of the circuit of FIG.
1
. Internal clock signal PCLKR is delayed with respect to input clock signal CLK by time interval TD
1
, as imposed by variable delay
122
. PCLKR is a preceding clock signal against the input clock signal CLK. The amount of preceding delay is the sum of delays TD
2
, TD
3
, TD
4
of the delay elements
142
,
144
,
146
respectively. Output data DATA_OUT from MCA
102
is synchronized with a PCLKR
2
signal, and transferred to group of DOUT Drivers
136
to output data DOUT, which is adjusted to a rising edge of the next cycle of input clock signal CLK.
Referring now to
FIG. 3
, another portion of device
100
is described. Some elements of device
100
are shown again, such as MCA
102
and input clock signal CLK.
Device
100
has a circuit
314
for locking a delay, so as to input groups of data into MCA
102
in a synchronized fashion. Circuit
314
is also known as a Delay Lock Loop (DLL) circuit.
Circuit
314
includes a variable delay circuit
322
, which is similar to circuit
122
. Variable delay circuit
322
receives input clock signal CLK, and an adjustment signal ADJ
3
. Variable delay circuit
322
outputs a write signal PCLKW, which is a delayed version from clock signal CLK. The delay is by a variable amount, which is controlled by adjustment signal ADJ
3
.
Circuit
314
also includes a phase detector
324
, which is similar to phase detector
124
. Phase detector
324
receives clock signal CLK and a feedback clock signal FCLK
3
. It will be recognized from the below that feedback clock signal FCLK
3
is generated from write signal PCLKW, after being subjected to some delays.
Phase detector
324
outputs the adjustment signal ADJ
3
. Adjustment signal ADJ
3
is such that the inputs of phase detector
324
are maintained in phase. In other words, the adjustment signal ADJ
3
is such that the phase of the feedback clock signal FCLK
3
is maintained to coincide with the phase of the input clock signal CLK.
Write signal PCLKW is output into a Data In (DIN) clock tree
362
of device
100
. DIN clock tree
362
may be made similarly to DOUT clock tree
132
of FIG.
1
.
From DIN clock tree
362
, write signal PCLKW is used to synchronize a group of DIN Latches
364
, as they receive input data DIN from a group of DIN pads
368
. The latched data is then input into MCA
102
.
As per the above,
FIG. 1
shows the case of X
8
bits. This means that group of DIN latches
364
is made from 8 DIN Latches
364
-
1
,
364
-
2
, . . . ,
364
-
8
.
It will be appreciated that DIN clock tree
132
contributes a delay. Without correction, this delay may result in not synchronizing the inputting of data.
Returning to circuit
314
, a feedback loop is further made, which starts from variable delay circuit
322
and ends in phase detector
324

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