Semiconductor devices and process for producing the same

Details Semiconductor devices and process for producing the same Semiconductor devices and process for producing the same

1998-12-30

2002-04-30

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S605000, C438S607000, C438S618000

Reexamination Certificate

active

06380064

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor device and a process for producing the same, more particularly to a technique of forming multilayered wiring.
Recently, multilayer wiring structures employed in highly integrated semiconductor devices are required to have reduced resistance in inter-wiring contacts (via contacts) and improved wiring reliability.
FIGS. 11
to
13
show, in cross-sectional views, a process for producing a conventional two-layer wiring, which will be described below step by step.
In Step A (see FIG.
11
), a silicon oxide film
52
is deposited as an insulating film to an appropriate thickness on the surface of a single crystal silicon substrate
51
by means of CVD (chemical vapor deposition) method. Next, a titanium (Ti) thin film
53
, a titanium nitride (TiN) thin film
54
, an aluminum (Al) alloy thin film
55
and a titanium nitride (TiN) thin film
56
are deposited successively on the surface of the silicon oxide film
52
by means of sputtering to form a first wiring layer
71
.
Subsequently, the thus formed first wiring layer
71
is subjected to patterning employing the conventional photolithographic technique, followed by dry etching to form a wiring pattern of the first wiring layer. It should be noted here that the aluminum alloy thin film
55
contains, in addition to pure aluminum, other metals or high-melting metals (e.g., Al—Si (1%)-Cu (0.5%), Al—Cu and Al—Mg).
Use of such aluminum alloys instead of pure aluminum can prevent electromigration and stress migration from occurring. Electromigration refers to migration of aluminum atoms due to the electron current, while stress migration refers to shifting of the sites where stress is induced by heat, and both phenomena can cause disconnection.
Further, the titanium thin film
53
and the titanium nitride thin film
54
formed under the aluminum alloy thin film
55
are to prevent adhesion at contact sections (not shown) between the aluminum alloy thin film
55
and the substrate
51
from being destroyed by the reaction between Al and Si. If these films
53
and
54
are not present, aluminum in the aluminum thin film
55
reacts with the silicon substrate
51
, when heat treatment is carried out after formation of the first wiring layer. Thus, while Al and Si form an eutectoid, the Si is supplied from the silicon substrate
51
, so that adhesion at each interface is destroyed. Accordingly, the titanium thin film
53
and the titanium nitride thin film
54
are formed under the aluminum alloy thin film
55
to prevent a reaction at each interface from occurring.
Further, the reason why the titanium thin film
53
is formed under the titanium nitride thin film
54
is that the contact resistance is increased if the titanium nitride film
54
only is formed. As described above, the titanium nitride thin film
54
and the titanium thin film
53
serve as barrier metals. Further, the titanium nitride thin film
56
formed on the aluminum alloy thin film
55
is to prevent the aluminum alloy thin film
55
, when subjected to photolithographic light exposure, from reflecting light. In other words, the titanium nitride thin film
56
serves as a reflection preventive film (cap metal).
In Step B (see FIG.
12
), a silicon oxide film
57
is deposited as a layer insulating film by means of CVD to an appropriate thickness on the surface of the titanium nitride thin film
56
of the first wiring layer, and patterning of contact holes is carried out by employing a conventional photolithographic technique, followed by formation of contact holes
58
by means of dry etching.
In Step C (see FIG.
13
), etching scum in the contact holes
58
and the oxide film present on the surface of the titanium nitride thin film
56
of the first wiring layer
71
in each contact hole
58
is removed by means of sputter etching employing an inert gas (e.g., argon).
Next, a titanium nitride thin film
59
, an aluminum alloy thin film
60
and a titanium nitride thin film
61
are deposited successively onto the surface of the silicon oxide film
57
and in the contact holes
58
to form a second wiring layer
72
.
Subsequently, the second wiring layer
72
is subjected to patterning employing a conventional photolithographic technique followed by dry etching to form a wiring pattern of the second wiring layer
72
to complete the process of producing the two-layer wiring. The aluminum alloy thin film
60
is of the same material as the aluminum alloy thin film
55
.
The titanium nitride thin film
61
formed on the aluminum alloy thin film
60
serves as a cap metal like the titanium nitride thin film
56
. Further, the titanium nitride thin film
59
formed under the aluminum alloy thin film
60
is to control growth of hillocks caused by heat treatment such as sintering and alloying. More specifically, since growth of hillocks induces short-circuiting in the wirings, the titanium nitride thin film
54
is formed under the aluminum alloy thin film
60
to control growth of hillocks.
However, in the prior art-exemplified above, while an increase in the contact resistance is controlled, for example, by forming the titanium thin film
53
under the titanium nitride thin film
54
in Step A, only the titanium nitride thin films
56
and
59
are present at contact portions between the first wiring layer and the second wiring layer.
Recently, semiconductor devices have become more and more integrated, so that contact holes
58
are required to have smallest possible diameters, and it is essential to prevent contact resistance between the first wiring layer and the second wiring layer from increasing. Under such circumstances, Japanese Unexamined Patent Publication No. 7-142580 describes a laminate structure. In this publication, titanium nitride thin film/titanium thin film is employed at contact portions between the first wiring layer and the second wiring layer, and while the function as cap metals is retained, contact resistance is lowered and electromigration resistance is improved.
Although the prior art semiconductor of the above Japanese publication has excellent contact resistance and electromigration resistance, it is slightly inferior, due to the additional formation of titanium thin film to semiconductors having a titanium nitride thin film only in serving the demand for finer or highly integrated wirings.
SUMMARY OF THE INVENTION
The present invention relates to a semiconductor device and a process for producing the same, and it is an objective of the present invention to provide a semiconductor device in which the thickness of wiring layers are reduced, while the cap metal retains its function, so as to achieve fining and higher integration of wirings, as well as, a process for producing the same.
In the process for producing the semiconductor device according to the present invention, wiring layers are formed on a semiconductor substrate, and the wiring layers are doped with an impurity.
The semiconductor device according to the present invention has a lower wiring layer and an upper wiring layer that are spaced away from each other. An insulating film is electrically insulating the lower wiring layer and the upper wiring layer from each other. The insulating film contains contact holes. The contact holes are packed with a wiring material for electrically connecting the lower wiring layer to the upper wiring layer. The lower wiring layer contains an impurity for reducing its resistivity.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principals of the invention.


REFERENCES:
patent: 4692385 (1987-09-01), Johnson
patent: 4823182 (1989-04-01), Okumura
patent: 5414301 (1995-05-01), Thomas
patent: 03-163875 (1991-07-01), None
patent: 04-014874 (1992-01-01), None
patent: 06-132286 (1994-05-01), None
Choi et al., Electrical Characteristics of TiB2 for ULSI Applications, pp. 2341-2345, (IEEE), 1992.*
T. Amazawa, Fully Planarized Four—

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