Semiconductor devices and methods for manufacturing the same

Details Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods for manufacturing the same

2001-03-27

2004-11-02

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S783000, C438S787000

Reexamination Certificate

active

06812123

ABSTRACT:

Japanese Patent Application No. 2000-086607, filed Mar. 27, 2000, is hereby incorporated by reference in its entirety. U.S. patent application Ser. No. 09/817,935 is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for manufacturing the same, including semiconductor devices having a characteristic structure of pad sections (external connection electrodes) and methods for manufacturing the same.
RELATED ART
FIG. 5
shows a cross-sectional view of one example of a conventional bonding pad section. In this example, a pad section
130
is formed in a specified region over an uppermost interlayer dielectric layer
120
that is formed from a PBSG. The pad section
130
is formed from a titanium layer
132
, a titanium nitride layer
134
and an aluminum alloy layer
136
. A passivation layer
140
is formed over surfaces of the interlayer dielectric layer
120
and the pad section
130
. An opening section
142
that forms a bonding region is formed in the passivation layer
140
. Wire bonding with, for example, a wire
150
is conducted in the opening section
142
.
The bonding pad structure can be formed in the same steps that are conducted to form the first wiring layer. More particularly, the uppermost interlayer dielectric layer
120
is formed in the same step conducted to form a first interlayer dielectric layer. The titanium layer
132
and the titanium nitride layer
134
that compose the pad section
130
are formed in the same steps that are conducted to form a barrier layer between an impurity diffusion layer formed in the semiconductor substrate and a contact section formed in the first interlayer dielectric layer. Further, the aluminum alloy layer
136
is formed in the same step to form the contact section and the first wiring layer.
PROBLEMS WITH THE RELATED ART
In the bonding pad structure shown in
FIG. 5
, when the bonding wire
150
is bonded to the pad section
130
, an exfoliation may occur near the interface between the pad section
130
and the interlayer dielectric layer
120
. This type of exfoliation is thought to take place because a weak layer such as a titanium oxide layer is formed near the interface between the titanium layer
132
and the interlayer dielectric layer
120
and thus the coherency between the interlayer dielectric layer
120
and the titanium layer
132
lowers.
SUMMARY
One embodiment relates to a semiconductor device including a pad section over an interlayer dielectric layer. The interlayer dielectric layer includes a first silicon oxide layer that is formed by a polycondensation reaction of a silicon compound and hydrogen peroxide, and a second silicon oxide layer formed over the first silicon oxide layer and containing an impurity. The pad section includes a wetting layer and a metal wiring layer.
Another embodiment relates to a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a interlayer dielectric layer, including (a) (1) forming a first silicon oxide layer by reacting a silicon compound and hydrogen peroxide through a chemical vapor deposition method, (a) (2) forming a second porous silicon oxide layer by reacting a silicon compound, at least one of oxygen and a compound including oxygen, and a compound including an impurity through a chemical vapor deposition method; (b) forming a wetting layer over the interlayer dielectric layer; (c) forming a metal wiring layer over the wetting layer; and (d) forming a pad section by patterning the wetting layer and the metal wiring layer.
Another embodiment relates to a method for manufacturing a semiconductor device, including forming a first silicon oxide layer using a polycondensation reaction of a silicon compound and hydrogen peroxide. The method also includes forming a second silicon oxide layer including an impurity therein. The method also includes forming a pad section over the first silicon oxide layer and the second silicon oxide layer, the pad section including a wetting layer and a wiring layer.


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Notice of Reasons of Rejection for Japanese Patent Application No. 2000-086607 (from which priority is claimed in U.S. Ser. No. 09/818,743), which lists JP10-233443, JP07-078821, JP09-092717, JP59-032143, JP03-227540, JP11-145134 and JP2000-100816.
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Notice of Reasons of Rejection for Japanese Patent Application No. 2000-086608 (from which priority is claimed in U.S. Ser. No. 09/817,935), dated Mar. 18, 2003, which lists JP10-233443 and JP59-172745.
U.S. application Ser. No. 09/817,935, filed Mar. 27, 2001—copy of application and drawings as filed and pending claims.

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