Semiconductor devices and methods for fabricating the same

Details Semiconductor devices and methods for fabricating the same Semiconductor devices and methods for fabricating the same

2004-01-15

2004-10-19

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S212000, C438S243000, C438S259000, C438S270000, C438S271000, C257S330000, C257S332000, C257S334000

Reexamination Certificate

active

06806174

ABSTRACT:

FIELD OF THE DISCLOSURE
The present disclosure relates generally to semiconductor devices and, more particularly, to methods for fabricating semiconductor devices.
BACKGROUND
In general, semiconductor devices may be divided into transistors, bipolar ICs (Integrated Circuits), and MOS ICs. A MOS (Metal Oxide Semiconductor) transistor is a type of field effect transistor. MOS transistors have the following structure: a source/drain region formed in a semiconductor substrate and a gate oxide layer and a gate formed on the substrate in which the source/drain region is formed. MOS transistors which have a LDD (Lightly Doped Drain) region inside the source/drain region are widely used.
MOS transistors may be further divided into N channel MOS transistors and P channel MOS transistors based on the type of channel in the device. A device with an N channel transistor and a P channel transistor formed on one substrate is called a CMOS (Complementary Metal Oxide Semiconductor) transistor.
A prior art method of fabricating a conventional semiconductor device will now be explained with reference to
FIG. 1
a
through
FIG. 1
d.
In the example of
FIG. 1
a
, an active region for a semiconductor device is defined with the formation of an STI (Shallow Trench Isolation) on a silicon wafer
1
. Selective ion implantation of P-channel and N-channel dopants into the defined active region forms an N well for the PMOS region and a P well for the NMOS region, respectively. Then, after a gate oxide layer
3
is formed by thermal oxidation of the silicon wafer
1
, polysilicon
4
is deposited on the layer by CVD (chemical vapor deposition).
The resistance of the polysilicon
4
is decreased by annealing after doping the P-channel dopant into the polysilicon of the PMOS region and the N-channel dopant into the polysilicon of the NMOS region, respectively.
Then, the gate electrode of the semiconductor device is formed by patterning the polysilicon
4
and the gate oxide layer
3
. The source/drain regions
5
with low concentration are formed by selective ion implantation of a P-channel dopant and an N-channel dopant with low concentration into the PMOS region and the NMOS region, respectively, with a mask of the gate electrode. Next, a nitride layer
6
is deposited on the entire surface of the silicon wafer
1
.
As illustrated in
FIG. 1
b
, the nitride layer
6
on the silicon wafer
1
is removed by blanket etching. Though the nitride layer is removed from the upper surface of the silicon wafer
1
, it is not removed from the lateral walls of the gate electrodes
3
and
4
, and, thus, forms spacers
6
. Then, source/drain regions
5
with high concentration are formed by selective ion implantation of P-channel dopant and N-channel dopant with high concentration into the PMOS region and NMOS region, respectively, with the gate electrodes
3
,
4
and the spacers
6
masked.
As illustrated in
FIG. 1
c
, a PMD (Pre-Metal Dielectric) liner oxide layer
8
is formed. The PMD liner oxide layer
8
prevents defects in the silicon wafer and the semiconductor device and diffusion of alkali ions into the silicon wafer since such defects and diffusion are caused by the high moisture contents of BPSG (Borophosphosilicate Glass) and PSG (Phosphosilicate Glass) layers which are deposited as interlayer dielectric in succeeding processes.
An interlayer dielectric
9
such as a BPSG or PSG layer is deposited for insulation between the metal layer and the polysilicon (or source/drain region). The metal layer is formed to connect the electrode of semiconductor device in succeeding processes. The interlayer dielectric
9
is planarized by a CMP (Chemical Mechanical Polishing) process to achieve satisfactory step coverage of the silicon wafer.
As illustrated in
FIG. 1
d
, a mask pattern is formed on the interlayer dielectric
9
to reveal the contact regions for the electrode connection of the semiconductor device. Then, the interlayer dielectric
9
revealed by the mask pattern is etched and removed. Since the revealed areas of the PMD liner oxide layer
8
are etched and removed, contact holes are formed to reveal the electrode regions (e.g., the gate electrodes and the source/drain regions) of the semiconductor device.
After the mask pattern remaining on the interlayer dielectric
9
is removed, a thin metallic film is deposited on the entire surface of the silicon wafer
1
by using sputtering to fill the contact holes with the thin metallic film. Then, as the thin metallic film on the dielectric is patterned, a metal wiring layer is formed. Finally, the semiconductor device is completed.
As miniaturization of semiconductor devices leads to miniaturization of design rules, several problems are caused for the conventional fabrication of semiconductor devices when the contacts with the gate and source/drain regions are formed.
As shown in
FIG. 1
, a conventional gate structure has non-planarization weak points and also has a failure possibility created by a gate to contact short due to a lack of gate contact margin due to the miniaturzation of the device. Furthermore, it is difficult to form a fine gate pattern because current control is achieved by controlling the gate CD (critical dimension).
U.S. pat. No. 4,455,740 describes a method of forming a trench gate structure that achieves a size reduction of the transistor and makes the source and drain closer.
Japanese patent publication No. JP6097450 describes a top drain trench type RESURF (Reduced Surface Field) DMOS (Diffusion Metal Oxide Semiconductor) transistor that forms a trench between the source and the drain and establishes a gate inside the trench.
ISPSD 2000, pages 47-50, describes a trench gate structure that fills the inside of the trench with a polysilicon gate.
Japanese patent publication No. JP
7
074352 describes a transistor for horizontal electric power by forming the source, drain, and trench on the substrate, and forming a gate on the surface of the region which forms a channel between the source and the trench.
A structure and operation of a trench DMOS transistor is discussed in Bulucea et al., “Trench DMOS Transistor Technology for High Current Switch”, 1991. Vol. 34, No. 5, pp. 493-507.
U.S. pat. No. 5,378,655 describes an erect gate structure for fabricating a trench gate power device.
Though such prior art efforts adopt a gate buried in a trench, creating a gate pattern is difficult in that the source/drain electrodes are both in the sides of a trench and that current control is achieved through the gate CD.


REFERENCES:
patent: 4455740 (1984-06-01), Iwai
patent: 4835585 (1989-05-01), Panousis
patent: 5108938 (1992-04-01), Solomon
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5639676 (1997-06-01), Hshieh et al.
patent: 5640034 (1997-06-01), Malhi
patent: 6509608 (2003-01-01), Hueting
patent: 6518129 (2003-02-01), Hueting et al.
patent: 6586800 (2003-07-01), Brown
patent: 2001/0041407 (2001-11-01), Brown
patent: 2003/0122163 (2003-07-01), Kitamura
patent: 2004/0002222 (2004-01-01), Venkatraman
patent: 06-097450 (1994-04-01), None
patent: 07-074352 (1995-03-01), None
C. Bulucea et al., Trench DMOS Transistor Technology For High-Current (100 A Range) Switching, Solid State Electronic, vol. 34, No. 5, pp493-507, 1991.

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