Semiconductor devices and manufacturing method thereof

Details Semiconductor devices and manufacturing method thereof Semiconductor devices and manufacturing method thereof

2000-07-13

2004-03-16

Fahmy, Jr., Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified encapsulant

C257S701000, C257S787000, C257S678000

Reexamination Certificate

active

06707166

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, the present invention relates to a semiconductor device which has a chip on board (COB) structure and to a method for manufacturing such a device.
BACKGROUND OF THE INVENTION
A chip on board (COB) is well known as a mounting structure which is fabricated without a molding to reduce costs.
A conventional COB structure is shown in FIG.
7
(A) and FIG.
7
(B). FIG.
7
(A) is a plane view of the COB structure and FIG.
7
(B) is a cross section view along the line
7
B—
7
B shown in FIG.
7
A). In FIG.
7
(A), an encapsulating material is not shown to facilitate understanding.
In the conventional structure, a semiconductor chip
1
is mounted on a substrate
2
by an adhesive
3
. The semiconductor chip
1
includes plural electrode pads
4
which are formed thereon and the substrate
2
has plural conductive pads
5
which are formed thereon. Conductive lines
6
, such as gold lines formed by a wire bonding apparatus, connect the electrode pads
4
with the conductive pads
5
.
The semiconductor chip
1
, the electrode pads
4
, the conductive lines
6
and connecting points between the conductive pads
5
and the conductive lines
6
are covered by an encapsulating material
7
, such as a resin. A wall
8
which surrounds the semiconductor chip
1
is used to contain the encapsulating material
7
.
For efficiency, a liquid type resin which has a low coefficient of viscosity is usually used as the encapsulating material
7
. That is, since the liquid type resin is fluid, an operation period is short, as compared with a resin having a high coefficient of viscosity. Further, a liquid type resin prevents air from being trapped therein in the encapsulating material. The wall
8
which prevents an outflow of the liquid type resin on the substrate is arranged in the periphery of the semiconductor chip. In this conventional example, the wall
8
is a frame which completely surrounds the semiconductor chip
1
.
In such a structure, since the liquid type resin has the low coefficient of viscosity, a surface of the resin is pulled toward the wall
8
as a result of a surface tension of the wall
8
. Thereby, a thickness of the resin inside of the wall
8
is thinner than that of the vicinity of the wall
8
.
When the conductive lines
6
are formed by the wire bonding apparatus, top portions
6
a
are formed in a part of the conductive lines
6
. As a result, the top portions
6
a
may be exposed in places where the thickness of the resin is small. Such exposure may result in corrosion of the conductive lines, thus reducing the quality of the semiconductor device.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a semiconductor device which prevents conductive lines from being exposed while maintaining a thin structure.
A second object of this invention is to provide a method for manufacturing such a device.
To achieve the object, one aspect of the invention includes a first wall and a second wall, wherein the first wall is arranged in a pad region which surrounds a chip region, the second wall is arranged on a semiconductor chip mounted in the chip region, and conductive lines are arranged between the first wall and the second wall and are encapsulated by a encapsulating material formed between the first and second walls.
According to another aspect of the invention, a cover is placed above a chip region and an encapsulating material is introduced into a space between the cover and the chip region.
According to the invention, as an influence of surface tension is restrained, occurrence of thin portions of the encapsulating material can be reduced. Therefore, exposure of the conductive lines is avoided while maintaining a thin structure.


REFERENCES:
patent: 4961105 (1990-10-01), Yamamoto
patent: 5036024 (1991-07-01), Mine et al.
patent: 5311060 (1994-05-01), Rostoker et al.
patent: 5539250 (1996-07-01), Kitano et al.
patent: 5962917 (1999-10-01), Moriyama
patent: 6048754 (2000-04-01), Katayama et al.
patent: 49-122974 (1974-11-01), None
patent: 5-218116 (1993-08-01), None

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