Semiconductor devices

Static information storage and retrieval – Read/write circuit – Erase

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307238, 365189, G11C 1140

Patent

active

042414245

ABSTRACT:
A novel mode of operation of an array of MNOS memory transistors is provided which employs the punch through mode of erase and enables a single transistor memory cell to be used. It being arranged that all `bits` are written into the `1` state and bits are selectively erased to provide the required data pattern.

REFERENCES:
patent: 3875567 (1975-04-01), Yamazaki
patent: 4099069 (1978-07-01), Cricchi et al.

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