Semiconductor device with well of different conductivity types

Details Semiconductor device with well of different conductivity types Semiconductor device with well of different conductivity types

1999-06-10

2001-03-27

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S378000, C257S532000

Reexamination Certificate

active

06207998

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device including wells of different conductivity types.
2. Description of the Background Art
Semiconductor devices having many transistors integrated are used in various electrical products such as workstations and personal computers.
A conventional DRAM employed as the main memory in a personal computer will be described hereinafter with reference to
FIG. 15
showing a partial sectional view thereof.
Referring to
FIG. 15
, a DRAM includes a P type well
2
, a P type well
3
, and an N type well
4
formed on a P type silicon semiconductor substrate
1
. The DRAM also includes an N type well
5
formed surrounding the sidewall of P well
2
, and an N type bottom N well
6
formed below P well
2
. The DRAM further includes an N channel MOS transistor
7
formed at P well
2
, an N channel MOS transistor
8
formed at P well
3
, and a P channel MOS transistor
9
formed at N well
4
.
The formation of a bottom N well in a conventional DRAM will be described with reference to FIG.
16
. In the conventional DRAM of
FIG. 16
, the area excluding the area where bottom N well
6
is to be formed is masked by a photo resist RE prior to formation of P wells
2
and
3
and N well
4
. N type ions are implanted from above P type semiconductor substrate
1
to form bottom N well
6
. The boundary between the portion where photo resist RE remains and the portion where photo resist RE is removed by an exposure•development step, i.e. the sidewall of photo resist RE, has a tapered configuration. Therefore, some of the N type ions will be introduced to the surface of the area where P well
3
is to be formed. If a transistor is formed at this area where N type ions are implanted, the transistor will not have the desired characteristics. Thus, a dead space was provided where no element is formed at the range within 4 &mgr;m from the boundary of bottom N well
6
.
SUMMARY OF THE INVENTION
An object of the present invention is to effectively utilize the dead space in the proximity of the bottom N well.
Another object of the present invention is to reduce power supply noise using a capacitor formed at a dead space.
According to the present invention, a semiconductor device includes a first well of a first conductivity type, a second well of a second conductivity type with a bottom well at the bottom portion, formed surrounding and in contact with the side portion and the bottom portion of the first well, a third well of the first conductivity type in contact with the second well and adjacent to the first well with the second well therebetween, and an MOS capacitor located at a boundary region between the second and third wells. The MOS capacitor is located at a boundary region of the second and third wells. The MOS capacitor includes an electrode formed on the third well with an insulation film therebetween, and an impurity region formed at the surface of the third well, receiving a predetermined voltage.
An advantage of the present invention is that, since the capacitor is provided in the proximity of the boundary between the third well and the second well including the bottom well, the region in the proximity of this boundary can be used effectively.
The semiconductor device of the present invention further includes a memory cell with a memory transistor of the second conductivity type formed at the first well, a fourth well of the second conductivity type opposite the second well with the third well therebetween, and a peripheral circuit with a transistor of the first conductivity type formed at the fourth well.
A sense amplifier is provided at a peripheral circuit. The sense amplifier includes a transistor of the first conductivity type and a transistor of the second conductivity type formed at the first well. A power supply line providing a sense amplifier potential and the capacitor are connected. Accordingly, variation in the potential of the power supply line occurring when the sense amplifier is activated can be suppressed without increasing the layout area. A semiconductor device that carries out a stable sense operation can be obtained.
Particularly, the peripheral circuit includes a word line driver having a transistor of the first conductivity type formed at the second well and a transistor of the second conductivity type formed at the first well.
Particularly, the first conductivity type is the P type, and the second conductivity type is the N type. A power supply potential is applied to the fourth well. A boosted potential higher than the power supply potential is applied to the second well.
Particularly, the first, second and third wells are formed at the semiconductor substrate of the first conductivity type. A substrate potential is applied to the electrode of the first conductivity type formed at the third well.
According to the present invention, a semiconductor device includes a first well of a first conductivity type, a second well of a second conductivity type with a bottom well at the bottom portion, formed surrounding and in contact with the side portion and the bottom portion of the first well, a third well of the first conductivity type in contact with the second well and adjacent to the first well with the second well therebetween, an isolation insulator located at the boundary region between the second well and the third well, and an MOS capacitor. The MOS capacitor includes an electrode formed on the third well with an insulation film therebetween, and in contact with the isolation insulator, and an impurity region formed at the surface of the third well, receiving a predetermined voltage.
A further advantage of the present invention is that, since a capacitor is provided in the proximity of the boundary between the third well and the second well including the bottom well, the region in the proximity of the boundary can be used effectively, and that proper operation can be carried out by forming the MOS capacitor so that the electrode is in contact with the isolation insulator.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5264723 (1993-11-01), Strauss
patent: 5361234 (1994-11-01), Iwasa
patent: 5373476 (1994-12-01), Jeon
patent: 5519243 (1996-05-01), Kikuda et al.
patent: 5838047 (1998-11-01), Yamauchi et al.
patent: 5930191 (1999-07-01), Jeon
patent: 6097067 (2000-08-01), Ouchi et al.
patent: 6104070 (2000-08-01), Matsumoto et al.
patent: 6-216332 (1994-08-01), None
patent: 7-086430 (1995-03-01), None
patent: 10-079484 (1998-03-01), None

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