Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-10
2003-10-28
Le, D (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S332000, C257S333000, C257S334000, C438S268000, C438S269000, C438S270000, C438S273000, C438S274000
Reexamination Certificate
active
06639275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device. More particularly, the invention relates to a semiconductor device having a structure of a vertical Field-Effect Transistor (FET), such as a vertical Metal-Oxide-Semiconductor FET (MOSFET), and a method of fabricating the device.
2. Description of the Related Art
Typically, vertical MOSFET structures have been used for power MOSFETs and Insulated-Gate Bipolar Transistors (IGBTs). In particular, if the drain-to-source withstand voltage of power MOSFETs is approximately 10 V to 60 V, power MOSFETs with their gate electrodes in a trench or trenches have been becoming the mainstream.
FIG. 1A
is a schematic, partial plan view of a prior-art semiconductor device of this type and
FIG. 1B
is a schematic, partial cross-sectional view along the line IB—IB in FIG.
1
A.
The prior-art semiconductor device of
FIGS. 1A and 1B
comprises a n
+
-type semiconductor substrate
111
on which a plurality of vertical MOSFETs
131
are formed. A n
−
-type epitaxial layer
112
is formed on the substrate
111
to cover its whole surface. The layer
112
serves as the common drain region for the MOSFETs
131
along with the substrate
111
.
In the surface area of the epitaxial layer
112
, a field dielectric
118
is selectively formed to define approximately rectangular active regions
132
on the substrate
111
. In each of the region
132
s
, a p-type diffusion layer
116
is formed in the surface area of the layer
112
. A lattice-shaped trench
113
is formed in the epitaxial layer
116
to penetrate vertically through the same, thereby forming device-formation regions on the substrate
111
. Thus, the diffusion layer
116
is divided into rectangular islands by the trench
113
, where the islands are arranged at specific intervals over the entire substrate
111
. Each of the islands constitutes a base region
116
a
. The trench
113
extends laterally toward the field dielectric
118
. The ends
113
a
of the trench
113
are located near the isolation dielectric
118
.
In the surface area of each base region
116
a
, n
+
-type diffusion regions
117
are formed to serve as source regions. Each of the source regions
117
has a frame-like plan shape running along the periphery of the corresponding base region
116
a
at a specified width.
Gate electrodes
115
, which are connected together, are formed in the trench
113
by way of corresponding gate dielectrics
114
. The gate dielectrics
114
, which are united together, cover the whole inner surface of the trench
113
and are located on the surface of the diffusion layer
116
outside the trench
113
. The gate electrodes
115
fill almost all the trench
113
while the tops of the electrodes
115
are exposed from the trench
113
.
A gate connection portion
115
a
having a specific pattern is formed to connect to the gate electrodes
115
. The portion
115
a
is located outside the trench
113
. Almost all the portion
115
a
is placed on the field dielectric
112
.
An interlayer dielectric layer
122
is formed on the p-type diffusion layer
116
to cover the gate electrodes
115
and the n
+
-type source regions
117
. The layer
122
has contact holes
120
and a contact hole
121
. The holes
120
are located over the respective base regions
116
a
to expose the corresponding base regions
116
a
and the corresponding source regions
117
. The hole
121
is located over the field dielectric
118
to expose the gate connection portion
115
a.
On the interlayer dielectric layer
122
, a source wiring layer
123
and a gate wiring layer
124
are formed. The source wiring layer
123
, which covers almost all the active region
132
, is mechanically and electrically connected to the base regions
116
a
and the source regions
117
by way of the contact holes
120
. The gate wiring layer
124
, which extends along the edge of the active region
132
over the field dielectric
118
, is mechanically and electrically connected to the gate connection portion
115
a
by way of the contact hole
121
.
The common drain region (which is formed by the combination of the substrate
111
and the epitaxial layer
112
), the source electrodes
117
, the gate dielectrics
114
, and the gate electrodes
115
constitute the vertical MOSFETs
131
connected in parallel on the substrate
111
.
P-n junctions are formed at the interfaces of the epitaxial layer
112
and the base regions
116
a
(i.e., the diffusion layer
116
) The layer
112
serves as an electric-field relaxation layer for relaxing the electric field applied to these p-n junctions, in addition to the function of the common drain region.
With the prior-art semiconductor device
100
, as explained above, the gate connection portion
115
a
formed on the field dielectric
118
outside the trench
113
is connected to the gate wiring layer
124
. This connection structure is based on the following reason.
Specifically, the gate electrodes
115
are formed by filling the trench
113
with a conductive material (e.g., n-type polysilicon) using a CVD (Chemical Vapor Deposition) method or the like. Thus, in order to suppress the required thickness of the conductive material for filling the trench
113
, the width of the trench
113
needs to be as much as approximately 1.0 &mgr;m or less. Moreover, the width of the trench
113
needs to be approximately uniform over the whole length of the trench
113
,
Therefore, if the gate wiring layer
124
is directly connected to the gate electrodes
115
, the size of the contact holes for electrically connecting the gate wiring layer
124
to the gate electrodes
115
will be as small as approximately 0.6 &mgr;m or less while taking the alignment margin in consideration. Since the gate wiring layer
124
is typically formed by sputtering or evaporating a metal such as aluminum (Al), the layer
124
will not be formed to fill such the small contact holes. This means that electrical connection of the layer
124
to the gate electrodes
115
is not realized. For this reason, the gate connection portion
115
a
is additionally provided outside the trench
113
for this purpose.
The prior-art device
100
has the following problem, because the gate connection portion
115
a
is located over the ends
113
a
of the trench
113
As shown in
FIG. 1B
, the p-type diffusion layer
116
has approximately right-angled top corners
116
b
at the ends
113
a
of the trench
113
. Thus, the thickness of the gate dielectric
114
near the top corners
116
b
will be thinner than that on other flat surfaces such as the bottom faces of the trench
113
. Furthermore, with the vertical MOSFET of this type, the gate dielectrics
14
are typically formed by a thin silicon dioxide (SiO
2
) layer with a thickness of approximately 10 to 100 nm generated by thermal oxidation.
Accordingly, if a voltage is applied across the p-type diffusion layer
116
and the gate connection portion
115
a
, dielectric breakdown of the gate dielectric
114
is likely to occur near the top corners
116
b
of the layer
116
. Thus, a problem that the gate withstand voltage of the MOSFET
131
is insufficient will arise.
This problem can be solved to some extent if a proper heat treatment such as wet oxidation at 1100° C. or higher is applied. This is because the corners
116
b
of the diffusion layer
116
are rounded due to high-temperature wet oxidation. However, high-temperature treatment will cause another problem that high-speed operation of the MOSFET
131
is difficult to be realized as desired. The reason of this problem is that high-temperature treatment makes it difficult for the MOSFET
131
to have a shallow structure, thereby restraining the reduction of the parasitic capacitance.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device that raises or improves the gate withstand voltage of a vertical FET, and a method of fabricating the device.
Another object of the present invention is to pro
Le D
NEC Corporaiton
Sughrue & Mion, PLLC
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