Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-31
2003-05-27
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S353000, C257S458000
Reexamination Certificate
active
06570231
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of producing a semiconductor device with a dual gate structure, including a metal suicide layer formed on the surfaces of a silicon gate electrode and a source/drain diffusion layer, and to a semiconductor device produced by the above-mentioned method. More particularly, it relates to a method of forming a gate electrode of a MOS transistor with a silicon gate electrode having a minimum width of about 0.35 &mgr;m or less.
2. Description of the Related Art
In recent years, for the purpose of enhancing the performance of semiconductor integrated circuit elements, a dual gate structure is adopted. In the dual gate structure, a silicon electrode into which n-type impurities are introduced is used for a gate electrode of an n-channel MOS transistor of a CMOS transistor, and a silicon electrode into which p-type impurities are introduced is used for a p-channel MOS transistor. In a semiconductor device with such a dual gate structure, an area that is not either n-type or p-type inevitably is present in the boundary portion of a silicon gate electrode formed from an n-channel region across to a p-channel region, and the resistance is rather high in the boundary portion. Therefore, with the silicon gate electrodes alone, it is difficult to conduct an electric current between the n-channel region and the p-channel region or to supply a common voltage.
In order to establish electrical connection between an n-type silicon gate electrode and a p-type silicon gate electrode, a metal silicide layer is formed on the surfaces of the silicon gate electrodes, and thus the electrical connection between the n-type silicon gate electrode and the p-type silicon gate electrode is established via the metal silicide layer.
The following is a description of a method of producing a CMOS semiconductor device with a conventional dual gate structure, including a metal silicide layer formed on the surfaces of a silicon gate electrode and a source/drain diffusion layer with reference to the drawings
FIGS. 8A and 8B
to
12
A and
12
B.
In
FIGS. 8A and 8B
, numeral
1
indicates an active region for an n-channel MOS transistor, on whose surface the n-channel MOS transistor is formed. Similarly, numeral
2
indicates an active region for a p-channel MOS transistor, on whose surface the p-channel MOS transistor is formed. Numeral
3
indicates an isolation insulating film for electrically isolating the transistors. In
FIG. 9A
, numeral
4
indicates a gate insulating film, and in
FIGS. 9A and 9B
, a silicon film
5
is deposited on the gate insulating film
4
.
N-type and p-type impurities are implanted into the silicon film
5
by ion implantation on the n-channel region side and the p-channel region side, respectively. As shown in
FIGS. 10A and 10B
, an area
6
containing almost no carriers contributing to electrical conductivity inevitably is present at the boundary between the n-channel active region and the p-channel active region.
When a gap between the region where an n-channel MOS transistor is to be formed (hereinafter referred to as “n-channel region”) and the region where a p-channel MOS transistor is to be formed (hereinafter referred to as “p-channel region”) is large, neither n-type nor p-type impurities are implanted into the area
6
because of a mask used for ion implantation. When the n-channel region and the p-channel region are in contact with each other, or the two regions overlap, the concentration of n-type impurities and that of p-type impurities, which contribute to electrical conductivity, are equal in the area. Thus, the area
6
inevitably is present, whether or not there is a gap between the n-channel region and the p-channel region.
FIGS. 10A and 10B
show an example without a gap between the two regions.
The silicon film
5
into which the above impurities are implanted is formed into a silicon gate electrode
7
by photolithography and etching. Thereafter, as shown in
FIGS. 11A and 11B
, a side wall insulating film
8
is formed on the side wall of the silicon gate electrode
7
in a self-aligned manner, an n-channel diffusion layer
9
is formed in the n-channel active region, and a p-channel diffusion layer
10
is formed in the p-channel active region. Then, a metal silicide layer
11
is formed on the surfaces of the silicon gate electrode and the active regions in a self-aligned manner, as shown in
FIGS. 12A and 12B
.
However, when the minimum width of the silicon gate electrode is about 0.35 &mgr;m or less, the following phenomena are likely to occur: Interfacial stress causes the metal silicide layer
11
to peel off partially from the surface of the silicon gate electrode
7
, and the metal silicide layer
11
thermally agglomerates locally on the silicon gate electrode
7
, so that some areas on the silicon gate electrode
7
are free from metal silicide. This makes it possible that the metal silicide layer is discontinued locally on some silicon gate electrodes. It is highly possible that such thermal agglomeration of the metal silicide occurs during the silicidation process by a heat treatment after depositing a metal film on the silicon gate electrode
7
, a heat treatment of the metal silicide layer for reducing the resistance in a short time, or a heat-treating process of an interlayer insulating film after forming the metal silicide.
Consequently, on the silicon gate electrode that connects the n-channel region and the p-channel region, when the discontinuity of the metal suicide layer is present in the high-resistance area at the boundary between the n-channel region and the p-channel region, the electrical connection between the two regions is lost, so that it is impossible to conduct an electric current in the boundary portion. This results in circuit failure, which seriously affects the operation of the circuit.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor device where a metal silicide layer is not discontinued and no circuit failure occurs, even when the minimum width of a silicon gate electrode is about 0.35 &mgr;m or less and a method of producing the same.
A semiconductor device of the present invention comprises at least one continuous electrode including a lower layer and an upper layer, formed on a semiconductor substrate. The lower layer includes a first portion of a p-type conductive layer, a second portion of an n-type conductive layer, and a high-resistance portion at the boundary between the first portion and the second portion. The upper layer is made of a metal silicide formed on the first portion, the second portion, and the high-resistance portion. The width of the electrode is larger in a region including the entire high-resistance portion than in a region not including the high-resistance portion.
According to this embodiment, even in a minute MOS transistor circuit with a silicon gate electrode having a minimum width of 0.35 &mgr;m or less, discontinuity in the metal silicide layer formed on the surface of the silicon gate electrode can be suppressed without significantly enlarging a circuit area by increasing the width of the silicon gate electrode only in the vicinity of the boundary between the n-channel region and the p-channel region. Thus, circuit failure caused by discontinuity in the metal suicide layer can be prevented.
Furthermore, in the semiconductor device of the present invention, it is preferable that the p-type conductive layer constitutes a gate electrode of a p-channel MOS transistor and the n-type conductive layer constitutes a gate electrode of an n-channel MOS transistor. This is because the same effects can be expected for CMOS semiconductor integrated circuit devices.
Furthermore, in the semiconductor device of the present invention, it is preferable that the metal silicide is titanium silicide, cobalt silicide or nickel silicide. This is because a heat treatment causes agglomeration in separate regions, that is, a silicide portio
Aono Kunitoshi
Fukumoto Tadashi
Matsuo Ichirou
Minemaru Takayuki
Ohtani Akihiko
Fahmy Wael
Ha Nathan W.
Matsushita Electric - Industrial Co., Ltd.
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