Semiconductor device with test mode for performing efficient...

Details Semiconductor device with test mode for performing efficient... Semiconductor device with test mode for performing efficient...

2001-10-25

2002-09-17

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

06452849

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a synchronous semiconductor memory device capturing an external signal in synchronism with a clock signal given periodically from outside the device. More particularly, the present invention relates to a test mode circuit in a synchronous dynamic random access memory (hereinafter referred to as SDRAN) using a data strobe signal (DQS) for capturing data.
2. Description of the Background Art
Although a dynamic random access memory (DRAM) used as a main memory has acquired a high speed in operation, but still, its operating speed cannot catch up an operating speed of a microprocessor (MPU). For this reason, it has been often said that an access time and a cycle time of a DRAM become bottlenecks, thereby reducing performance of all the system. In recent years, there has been proposed a double data rate SDRAM (DDR SDRAM) operating in synchronism with a clock signal as a main memory for a high speed MPU.
As a higher speed operation becomes possible, a test for confirming operation of a semiconductor memory device is harder to perform.
FIG. 20
is a diagram for describing a test for confirming functions of a semiconductor memory device.
Referring to
FIG. 20
, a semiconductor memory device
712
is confirmed on its operation by a tester
700
. Tester
700
includes: a timing generator
702
; a signal generator
704
generating an input signal to semiconductor memory device
712
according to an output of timing generator
702
; and a driver
706
driving an input node of semiconductor memory device
712
according to an output of signal generator
704
. Driver
706
gives semiconductor memory device
712
complementary clock signals extCLK and ext/CLK, control signals /RAS and /CAS, complementary strobe signals DQS and /DQS, and a data input signal DIN.
Semiconductor memory device
712
outputs a data output signal QOUT according to a signal given from tester
700
.
Tester
700
includes: a comparator
710
performing a level determination on a signal outputted from the semiconductor memory device
712
with a predetermined threshold value; and a determination section
708
performing determination by comparing an output from comparator
710
with an expected value pattern at a timing given from timing generator
702
.
FIG. 21
is an operating waveform diagram for describing input and output waveforms in a standardized operation of DDR SDRAM.
In
FIG. 21
, there is shown a write or read operation for consecutive
4
data (a total of 32 bits of 8×4) in an SDRAM capable of inputting and outputting of 8 bit data (byte data) at data input/output terminals DQ
0
to DQ
7
. The number of bits of data read out consecutively is referred to a burst length and the burst length can be usually changed by setting of a mode register in a DDR SDRAM.
Referring to
FIG. 21
, at a time point t
1
, control signals from the outside (a row address strobe signal /RAS, a column address strobe signal /CAS, an address signal Add. and so on) are captured at a rise edge of the clock signal extCLK. Since row address strobe signal /RAS is at L level in an active state, address signal Add. at this time is captured as a row address Xa. Note that address signal Add. includes address signals A
0
to A
10
and a bank address signal BA.
At a time point t
2
, the column address strobe signal /CAS goes to L level in an active state and captured into the interior of the DDR SDRAM in synchronism with a rise of clock signal ext.CLK. Address signal Add at this time is captured as a column address Yb. A column or row select operation is performed in DDR SDRAM according to row address Xa and column address Yb captured.
D/Q shows data signals DQ
0
to DQi inputted and outputted from an input/output terminal. After predetermined clock cycles (in
FIG. 21
,
3
.
5
clock cycles) passes away from a fall of row strobe address /RAS to L level, first data q
0
is outputted at a time point t
4
and data q
1
to data q
3
are consecutively outputted, following data q
0
.
Outputting the data q
0
to q
3
is performed in response to a crossing point between clock signal extCLK and clock signal ext/CLK. In order to enable high speed data transfer, data strobe signal DQS is outputted in phase with output data.
Note that at a rise edge of clock signal extCLK, which is a time point t
3
, control signals /RAS and /WE are set to L level and rewrite (precharge) to a memory cell is performed.
Signal waveforms at a time point t
5
or later show a write operation. At time point t
5
, row address Xc is captured. At a time point t
6
, column address strobe signal /CAS and write enable signal /WE are both set to L level in an active state and at the time, column address Yd is captured at a rise edge of clock signal extCLK. Data d
0
having been given at the time is captured as first write data. In response to falls of row address strobe signal /RAS and column address strobe signal /CAS, row and column select operations are performed inside DDR SDRAM. Hereinafter, input data dl to d
3
are sequentially captured in synchronism with data strobe signal DQS and written into respective corresponding memory cells.
As an operating speed of a semiconductor device increases, the accuracy of a tester in test on confirmation of its operation becomes problematic. In tester
700
described in
FIG. 20
, calibration is performed in order to keep a state of the tester constant. For example, this is because, if shifts in timing exist between plural control signals given to a semiconductor memory device from the tester, an inspection yield decreases.
Generally speaking, testers used in mass production or the like are each operated on many of devices simultaneously. Such a tester performing simultaneous measurement on many devices suffers from its lowered accuracy due to large numbers of driver pins and comparator pins. Contrary to this, most of testers for use in evaluation of a device in the development stage, where a small number of devices can be simultaneously measured therewith, have good accuracy due to the small number of measured devices. Therefore, it is conceived that a device with known characteristics having been measured by a high accuracy tester is used for calibration of a tester for mass production operative on simultaneous measurement of many of devices. That is, in this case, a standard device having known measurements is used and adjustments on a low accuracy tester are performed so as to output the same value as from the standard device.
For example, in a case of DDR SDRAM, data signal DQ is captured with data strobe signal DQS. Therefore, a set-up time and a hold time of data, which has been measured with a high accuracy tester, are measured by the low accuracy tester and phase matching on the low accuracy tester is performed. Then, a difference in output timing between a driver of a tester outputting data strobe signal DQS and a driver of a tester outputting data signal DQ can be narrowed.
However, there exist items that cannot be matched only by adjustments on device characteristics.
FIG. 22
is an operating waveform diagram showing relationships among clock signals CLK and /CLK, data strobe signals DQS and /DQS and data signal DQ in an ideal case.
Referring to
FIG. 22
, clock signal CLK and clock signal /CLK are crossed at a point of just a half amplitude of the waveforms. This applies to a relationship between data strobe signal DQS and data strobe signal /DQS in a similar manner.
FIG. 23
is an operating waveform diagram for describing a case where there arises a shift between waveforms of complementary signals.
Referring to
FIG. 23
, there is shown a case where clock signal /CLK lags behind clock signal CLK by some in respect to phase. Similar to this, data strobe signal /DQS lags behind data strobe signal DQS by some in respect to phase.
In a case where as shown in
FIG. 23
, clock signals CLK and /CLK are shifted from each other in respect to phase, the shift cannot be detected using a standard device

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