Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-10-11
2004-09-21
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S734000
Reexamination Certificate
active
06795943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, particularly to a semiconductor device with a plurality of first test modes and a plurality of second test modes.
2. Description of the Background Art
Semiconductor memories such as DRAMs and SRAMs are conventionally provided with a test mode to carry out an operation in addition to the normal write/read operation. The test mode is mainly classified into a test mode A carried out at the manufacturer side and a test mode B carried out at the user side.
At the manufacturer side, only four data input/output terminals among 16 data input/output terminals, for example, of a semiconductor memory are connected to the tester for testing in order to increase the number of semiconductor memories that can be tested simultaneously by one tester to reduce the test cost. Specification of test mode A is effected without using the data input/output terminal.
FIG. 12
shows a method of setting test mode A. Referring to
FIG. 12
, transition from the normal mode of the general write/read operation to test mode A is effected by applying to a terminal a high super VCC potential SVIH that is sufficiently higher than a power supply potential VCC and the so-called address key. Test mode A includes m (m is an integer of at least 2) modes
1
-m. Upon entering test mode A, any of modes
1
-m is selected and executed. Transition from test mode A to the normal mode is effected by executing a test mode reset sequence.
At the user side, the test mode is set in the normal usage status where all the 16 data input/output terminals are connected to, for example, a memory controller. It is difficult to obtain additionally a power supply for super VCC potential SVIH at the user side. Accordingly, specification of test mode B is effected using the data input/output terminal.
FIG. 13
shows a method of setting test mode B. Referring to
FIG. 13
, transition from the normal mode to test mode B is effected by entering an address key. Test mode B includes n (here, n is an integer of at least 2) modes
1
-n. After entering test mode B, any of modes
1
-n is selected and executed using 8 data input/output terminals in addition to the address key. Transition from test mode B to the normal mode is effected by executing a test mode reset sequence.
It is to be noted that in the conventional method of setting test modes A and B, only 4 out of sixteen data input/output terminals of a semiconductor memory are connected to the tester for testing at the manufacturer side. There was a problem that test mode B that uses 8 data input/output terminals cannot be set.
SUMMARY OF THE INVENTION
In view of the foregoing, a main object of the present invention is to provide a semiconductor device that can easily have a user-oriented test mode set using a tester.
According to an aspect of the present invention, a semiconductor device includes a first select circuit selecting any of a plurality of first test modes according to a signal applied via a plurality of first signal terminals, a second select circuit selecting any of a plurality of second test modes according to a signal applied via a plurality of second signal terminals, a third select circuit selecting any of the plurality of second test modes according to a signal applied via a plurality of third signal terminals, a fourth select circuit selecting a second test mode selected by both the second and third select circuits when a control signal is at a first level, and selecting a second test mode selected by the second select circuit when the control signal is at the second level, and a test mode execution circuit executing a first test mode selected by the first select circuit and a second test mode selected by the fourth select circuit. Therefore, by providing a plurality of first signal terminals and a plurality of second signal terminals to the tester, and setting the control signal at the second level, a desired second test mode can be executed without having to connect a plurality of third signal terminals to the tester. Therefore, a second test mode for the user can be easily executed using the tester.
Preferably, the first select circuit drives the control signal to the second level when a predetermined first test mode is selected among the plurality of first test modes, and drives the control signal to the first level when a first test mode other than the predetermined first test mode is selected. In this case, the control signal can be driven to the second level by selecting a predetermined first test mode.
Preferably a fourth signal terminal to input a control signal is provided. In this case, the level of the control signal can be set easily from an external source via the fourth signal terminal.
Preferably, the semiconductor device further includes a first signal generation circuit driving a first activation signal to an activation level in response to application of a predetermined first signal via a plurality of first signal terminals, and a second signal generation circuit driving a second activation signal to the activation level in response to application of a predetermined second signal via the plurality of first signal terminals. The first select circuit is rendered active in response to activation of the first activation signal. The second and third select circuits are rendered active in response to activation of the second activation signal. Here, the first select signal is rendered active only in the case where the predetermined first signal is input, and the second and third select circuits are rendered active only when the predetermined second signal is input. Therefore, the problem of a test mode being accidentally set can be prevented.
Further preferably, the semiconductor device includes a reset circuit resetting the first signal generation circuit in response to selection of any of the plurality, of second test modes and driving the first activation signal to an inactivation level. Since the first test mode is canceled in response to selection of the second test mode, the second test mode can be executed with priority over the first test mode.
Preferably, the reset circuit does not reset the first signal generation circuit when the control signal is at the second level. This can prevent the first signal generation circuit from being reset to cancel the first test mode when the control signal is driven to the second level by a predetermined first test mode.
Preferably, the semiconductor device is a semiconductor memory device. The semiconductor memory device includes a plurality of memory circuits, each preassigned with a unique address signal, a decoder selecting any of the plurality of memory circuits according to an address signal applied through a plurality of first signal terminals, and a data input/output circuit that transfers a data signal between a plurality of second and third signal terminals and a memory circuit selected by the decoder. The present invention is particularly advantageous in such a case.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5034923 (1991-07-01), Kuo et al.
patent: 5416740 (1995-05-01), Fujita et al.
patent: 6310807 (2001-10-01), Ooishi et al.
patent: 08-031197 (1996-02-01), None
Makabe Ryu
Sato Hirotoshi
Tsukude Masaki
McDermott Will & Emery LLP
Renesas Technology Corp.
Tu Christine T.
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