Semiconductor device with strain relieving bump design

Details Semiconductor device with strain relieving bump design Semiconductor device with strain relieving bump design

2007-04-24

2007-04-24

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S781000, C257S782000, C257S784000, C257S751000, C439S081000

Reexamination Certificate

active

10909124

ABSTRACT:
A semiconductor device (51) is provided. The device (51) comprises a die (53) having a contact pad (61) thereon, a redistribution conductor (59) having a base portion (64) which is in electrical communication with the contact pad (61) and a laterally extending portion (63), a bumped contact (65) which is in electrical communication with the redistribution conductor (59), and a passivation layer (57) disposed between the laterally extending portion (63) of the redistribution conductor (59) and the die (53). Preferably, the redistribution conductor (59) is convoluted and is adapted to peel or delaminate from the passivation layer (57) under sufficient stress so that it can shift relative to the passivation layer (57) and base portion (64) to relieve mechanical stress between substrate (69) and the die (53). Bump and coiled redistribution conductor (59) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.

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John C. Carson, “Advances in Chip Level Packaging” (2002 Lecture notes, Johns Hopkins University).
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D. Light, D. Castillo, M. Beroz, M. Nguyen, and T. Wang, “Vertical Expansion (WAVE) Packaging Process Development” (published by Tessera Technologies, 2001).
Joseph Fjelstad, “Strategies for Creating Compliant IC Packages at Near Chip Size” (INTERPACK 1999).
K. Klein, T. Leichle, E. Moss, P. Sassone and X. Wei, “A Survey of Compliant Interconnects for Wafer Level Packaging” (Dec. 13, 2001).

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