Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2003-04-07
2004-11-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S201000
Reexamination Certificate
active
06816426
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device having dynamic memory, such as a DRAM device. More particularly, the invention relates to such a semiconductor device that includes a self refresh test mode in which self refresh is monitored and/or modified by an external testing device. The invention also includes a method for constructing such a semiconductor device.
2. State of the Art
DRAMS (dynamic random access memory) include numerous cells in which data are stored. Such cells may include capacitive elements to which a charge is applied to signify a high or low voltage. However, because of leakage, the voltage of the charge decreases over time, making the contents of the cells unreliable. Refresh involves reading a datum from a cell before the datum becomes corrupted and rewriting the datum into the cell. The read and rewriting process may be essentially simultaneous.
There are various types of DRAM devices and various types of refresh. DRAMs are often referred to as either “standard refresh” or “extended refresh.” Whether a DRAM is a standard refresh or an extended refresh device may be determined by dividing the specified refresh time by the number of cycles. Table 1 lists some of the standard DRAMs that have been marketed by Micron Technology, Inc., assignee of the present invention, and their refresh specifications:
REFRESH
DRAM
TIME
NO. OF CYCLES
REFRESH RATE
4 Meg × 1
16 ms
1,024
15.6 &mgr;s
256K × 16
8 ms
512
15.6 &mgr;s
256K × 16
64 ms
512
125 &mgr;s
(L Version)
4 Meg × 4
32 ms
2,048
15.6 &mgr;s
(2K)
4 Meg × 4
64 ms
4,096
15.6 &mgr;s
(4K)
DRAMs having refresh rates of 15.6 &mgr;s are standard refresh devices, while DRAMs having refresh rates of substantially greater than 15.6 &mgr;s/row are extended refresh devices.
Two basic means of performing refresh are distributed and burst refresh. Distributing the refresh cycles so that they are evenly spaced is known as distributed refresh. When not being refreshed, the DRAM may be read from or written to. In distributed refresh, the DRAM controller is set up to perform a refresh cycle, for example, every 15.6 &mgr;s. Usually, this means the controller allows the current cycle to be completed, and then holds off all instructions while a refresh is performed on the DRAM. The requested cycle is then allowed to resume. Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until all rows have been accessed. During refresh, other commands are not allowed.
Different cycles may be used to refresh DRAMs, all of which may be used in a distributed or burst method. Standard refresh types include (1) {overscore (RAS)}-ONLY refresh, (2) {overscore (CAS)}-BEFORE-{overscore (RAS)} (CBR) refresh, and (3) Hidden refresh. To perform a {overscore (RAS)}-ONLY refresh, a row address is put on the address lines and then {overscore (RAS)} is dropped. When {overscore (RAS)} falls, that row will be refreshed and, as long as {overscore (CAS)} is held high, the Dqs will remain open.
The DRAM controller provides addresses of cells to be refreshed. The row order of refreshing does not matter as long as each row is refreshed in the specified amount of time.
A CBR refresh cycle is performed by dropping {overscore (CAS)} and then dropping {overscore (RAS)}. One refresh cycle will be performed each time {overscore (RAS)} falls. WE (write enable) is held high while {overscore (RAS)} falls. The Dqs will remain open during the cycle. In the case of CBR refresh, an internal counter is initialized to a random count when the DRAM device is powered up. Each time a CBR refresh is performed, the device refreshes a row based on the counter, and then the counter is incremented. When CBR refresh is performed again, the next row is refreshed and the counter is incremented. The counter will automatically wrap and continue when it reaches the end of its count. There is no way to reset the counter. Row addresses are not externally supplied or monitored. {overscore (CAS)} is held low before and after {overscore (RAS)} falls to meet
t
CSR and
t
CHR. {overscore (CAS)} may stay low and only {overscore (RAS)} toggles. Every time {overscore (RAS)} falls, a refresh cycle is performed. {overscore (CAS)} may be toggled each time, but it is not necessary. The address buffers are powered-down because CBR refresh uses the internal counter and not an external address. For power sensitive applications, this may be a benefit, because there is no additional current used in switching address lines on a bus, nor will the DRAMs pull extra power if the address voltage is at an intermediate state. Because CBR refresh uses its own internal counter, there is not a concern about the controller having to supply the refresh addresses.
In Hidden refresh, the user does a READ or WRITE cycle and then, leaving {overscore (CAS)} low, brings {overscore (RAS)} high (for minimum of
t
RP) and then low. Since {overscore (CAS)} was low before {overscore (RAS)} went low, the part will execute a CBR refresh. In a READ cycle, the output data will remain valid during the CBR refresh. The refresh is “hidden” in the sense that data-out will stay on the lines while performing the function. READ and Hidden refresh cycles will take the same amount of time:
t
RC. The two cycles together take 2×
t
RC. A READ followed with a standard CBR refresh (instead of a Hidden refresh) would take the same amount of time: 2×
t
RC.
A self refresh mode helps maximize power savings in DRAMS and provide a very low-current data-retention mode. Low-power, extended-refresh DRAMs (LPDRAMs) have the same functionality as a standard DRAM, except they have been tested to meet the lower CMOS standby current and the extended refresh specifications. Self refresh DRAMs, on the other hand, require additional circuitry to be added to the standard DRAM to perform the self refresh function.
Self refresh mode provides the DRAM with the ability to refresh itself while in an extended standby mode (sleep or suspend). It is similar to the extended refresh mode of an LPDRAM except the self refresh DRAM utilizes an internally generated refresh clock while in the self refresh mode. During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh signals. Therefore, it is no longer necessary to power-up the DRAM controller while the system is in the suspend mode. Consulting the devices' data sheets will determine the power savings achieved.
Self refresh may employ parameters
t
RASS,
t
CHD and
t
RPS. The DRAM's self refresh mode is initiated by executing a {overscore (CAS)}-BEFORE-{overscore (RAS)} (CBR) refresh cycle and holding both {overscore (RAS)} and {overscore (CAS)} LOW for a specified period. The industry standard for this value is 100 &mgr;s minimum (
t
RASS). The DRAM will remain in the self refresh mode while {overscore (RAS)} is LOW. Once {overscore (CAS)} has been held LOW for
t
CHD, {overscore (CAS)} is no longer required to remain LOW and becomes a “don't care.”
The self refresh mode is terminated by taking {overscore (RAS)} HIGH for
t
RPS (the minimum time of an operation cycle). Once the self refresh mode has been terminated, the DRAM may be accessed normally.
Self refresh may be implemented in both a distributed method and a wait and burst method. In a system that utilizes distributed CBR refresh as the standard refresh, accesses to the DRAM may begin as soon as self refresh is exited. The first CBR pulse should occur immediately prior to active use of the DRAM to ensure data integrity. Since CBR refresh is commonly implemented as the standard refresh, this ability to access the DRAM immediately after exiting self refresh is a big benefit over the burst scheme described later. If anything other than CBR refresh is used as the standard refresh, a burst of all rows should be executed when exiting self refresh. This is because the CBR counter and the DRAM controller cou
Elms Richard
Hur J. H.
Micro)n Technology, Inc.
TraskBritt
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