Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-02-12
2001-06-05
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S721000, C438S744000
Reexamination Certificate
active
06242354
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to a Metal Oxide Semiconductor (MOS) integrated circuit and method of fabrication thereof, and more specifically to a MOS transistor structure with self-aligned contacts and a method for the fabrication of thereof with integrated silicide stringer removal.
2. Related Art
Self-ALigned metal silICIDE contact structures, commonly referred to as salicide structures, are often used in the formation of Metal Oxide Semiconductor (MOS) transistor structures to minimize contact resistance. Thus, allowing for reduction of the size of contact structures. While the formation of these salicide structures require several process steps, advantageously, none is a masking step; hence, processes for the formation of salicide structures are widely used.
In one known salicide process for a MOS transistor, source and drain (S/D) regions are formed aligned to a gate electrode structure and/or any sidewall spacers that may be used. A blanket metal layer is deposited so that silicon, at the upper surface of source, drain and gate regions, is in contact with the metal. The wafer is then heated to a temperature sufficiently high for the metal and silicon, in contact with one another, to undergo a reaction and form a metal silicide. The unreacted metal is then removed, and regions of metal silicide are revealed. Thus, by employing a salicide process, regions of metal silicide are formed aligned, without benefit of a masking step, in this example as S/D and gate regions. These silicide regions, formed without masking steps, are referred to as self-aligned regions. During the salicide process the sidewall spacers serve to provide sufficient spacing to prevent bridging of the gate silicide region with either the source or drain silicide regions. Often, one or more optimizations or process modifications are used to help prevent metal bridging, commonly referred to as stringers. After removal of the unreacted metal, a second, higher temperature silicide anneal step is often employed to stabilize the silicide regions formed and to provide the lowest possible silicide resistivity.
However, further reductions in device geometries, for example to meet the demand for higher performance, necessarily reduces the size of the sidewall spacers. These smaller sidewall spacers are then less able to provide adequate spacing between adjacent regions during silicide formation and increased metal bridging or stringers result. While stringer formation occurs due to a variety of reasons, reduced spacer size results in the various optimizations or process modifications used to alleviate the problem being less successful. Thus the yield loss due to electrical shorts caused by such stringers increases.
While the reduced device geometries often result in a lower device yield, as discussed above, the full benefit of the geometry reductions is typically not realized. Referring to
FIG. 1A
, a plan view of a portion of a transistor formed in a semiconductor substrate, in the manner of the prior art, is shown. Prior art transistor
200
has a gate structure
300
having a gate electrode region
304
. Gate electrode region
304
crosses over an active area
260
having source and drain (S/D) regions
240
formed therein. Gate region
304
and S/D regions
240
define a channel region
400
, (indicated with dashed lines). Where maximum performance is desired for transistor
200
, region
304
is formed having a gate length
310
that is the minimum dimension achievable within the process technology employed. In this manner, device performance is enhanced, as compared to transistors having larger gate lengths
310
. However, where a prior art transistor
200
has a minimum dimension gate length
310
, gate electrode region
304
does not provide sufficient space for electrical contact and an additional gate contact region
302
is needed.
Gate contact region
302
has a contact hole
220
. Contact hole
220
is formed in a dielectric layer (not shown) that overlies the substrate (not shown) and all of transistor
200
. Contact hole
220
has edges
225
that are spaced a distance
204
from edges
305
of gate contact region
302
to form a buffering region
230
about hole
220
. This additional space or buffering region
230
serves to provide an area that accommodates normal photolithographic and etch process variations in positioning and forming contact hole
220
, while ensuring that hole
220
always falls within region
302
. Thus, rather than a direct contact to region
304
, electrical contact to region
304
is made in an indirect manner, through region
302
and prior art transistors
200
can not achieve a minimum total surface area.
Turning to
FIG. 1B
, a transistor
500
having direct gate contact is shown being formed with the prior art process. Process buffering regions
530
are provided to allow positioning of a gate contact hole
520
within the boundaries of a gate electrode region
504
. As a result, gate length
610
is necessarily larger that minimum gate length
310
(
FIG. 1A
) of prior art transistor
200
(FIG.
1
A), as it includes buffering regions
530
. Thus,while transistor
500
may use less area than transistor
200
, larger gate length
610
will result in reduced performance for transistor
500
ans compared to transistor
200
. Therefore, transistors formed in the manner of the prior art can not simultaneously achieve both maximum transistor performance and minimum surface area.
Thus, it would be advantageous to form an MOS transistor having self-aligned silicide enhanced contact regions that are free of silicide stringers and have direct electrical coupling to selected silicide regions within the boundaries of the device. In addition, it would be advantageous to have a method for forming such an MOS transistor without adding any masking steps to those for a standard MOS transistor fabrication method. Finally, it would be advantageous for the transistor and method for forming, thereof, to allow a choice of transistor isolation processes, for example a local oxidation of silicon (LOCOS) process or a trench isolation process.
SUMMARY
In accordance with the present invention, an MOS transistor having self-aligned silicide enhanced contact regions that are free of silicide stringers and having electrical coupling to selected silicide regions within the device boundaries, and method of fabrication thereof, are enabled. A gate electrode structure is provided overlying a semiconductor substrate. In some embodiments, the gate electrode structure is a minimum device geometry. Sidewall spacers are formed adjacent to the gate electrode and provide spacing between the subsequently formed S/D regions and the areas under the gate electrode structure. A source and a drain region are formed within the substrate, these S/D regions aligned to the gate electrode structure. In some embodiments a metal layer is formed overlying exposed areas of the gate electrode and S/D regions and the substrate is heated to a temperature sufficiently high for the metal layer to react and form silicide regions in the exposed areas. In some embodiments of the present invention, metal gate electrodes are employed and no silicide region overlying the gate electrode is formed.
After formation of the silicide regions, at least some portion of the sidewall spacers are removed selectively with respect to any like material in isolation or other regions. Thus removing or “lifting-off” silicide stringers that may have formed.
After stringer removal, a conformal etch-stop layer is deposited overlying the substrate and including the gate electrode structure, followed by deposition of a dielectric layer. The conformal layer is selected such that it etches selectively with respect to the dielectric layer and isolation regions. In some embodiments the dielectric layer is planarized, a masking layer formed thereon and patterned, and the dielectric layer etched to form contact holes which expose underlying portions of the etch-stop layer. In other embodiments the dielectric layer is patterned
Chaudhuri Olik
Coleman William David
Kwok Edward CX.
National Semiconductor Corporation
Skjerven Morrill & MacPherson LLP
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