Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-01-03
2001-01-23
Picard, Leo P. (Department: 2835)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S751000, C257S768000, C257S689000, C257S387000
Reexamination Certificate
active
06177701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device including a resistor and an active component such as a bipolar transistor and a Field-Effect Transistors (FET), and a fabrication method of the device.
2. Description of the Prior Art
With the fabrication of a semiconductor device termed a “gate array”, a semiconductor substrate including active and passive components therein is prepared in advance. The components are arranged in the form of an array. Then, customized interconnection layers are formed on or over the active and/or passive components to electrically interconnect the related components. Thus, an integrated circuit device having specific functions is fabricated according to the need of a customer.
FIG. 1
shows a schematic plan view of a resistor used for the semiconductor device of this sort.
In
FIG. 1
, the resistor is made of a patterned polysilicon layer
121
with a rectangular plan shape. The layer
121
is doped with an n- or p-type impurity to realize a wanted conductivity. Two contact areas
122
are formed on the layer
121
near its opposite ends, respectively. The width of the layer
121
is W, and the distance between the contact areas
122
is L.
When the sheet resistance of the doped polysilicon layer
121
is defined as &rgr;
s
, and the contact resistance of the layer
121
at the contact areas
122
is defined as R
c
, the resistance R of the polysilicon resistor is expressed as the following equation (1).
R=&rgr;
s
(
L/W
)+2
R
c
(1)
A conventional semiconductor device including the polysilicon resistor of
FIG. 1
is shown in
FIG. 2
, which is, for example, disclosed in the Japanese Non-Examined patent Publication No. 3-22562 published in January 1991. Although this semiconductor device has a plurality of bipolar transistor regions and a plurality of resistor regions, only one bipolar transistor region and only one resistor region are explained here for the sake of simplification.
As shown in
FIG. 2
, this semiconductor device includes a bipolar transistor region
130
having an npn-type bipolar transistor and a resistor region
131
having a resistor.
An n-type single-crystal silicon (Si) epitaxial layer
104
is formed on the surface of a p-type single-crystal silicon substrate
101
. An n-type buried layer
102
is formed near the interface of the substrate
101
and the epitaxial layer
104
. A p-type insulating layer
103
is selectively formed in the epitaxial layer
104
. The bottom of the layer
103
is extended to the inside of the substrate
101
.
A field oxide layer
105
of silicon dioxide (SiO
2
) is selectively formed in the surface are of the epitaxial layer
104
for electrical isolation. The bipolar transistor region
130
is electrically isolated from the resistor region
131
and other device regions (not shown) adjacent to the region
130
.
In the transistor region
130
, an n
+
-type collector connection region
106
, a p-type extrinsic base region
107
, and a p-type intrinsic base region
108
, an n-type emitter region
109
are formed in the epitaxial layer
104
.
A SiO
2
layer
110
is formed on the field oxide layer
105
and the exposed epitaxial layer
104
. A contact window
124
is formed in the SiO
2
layer
110
to expose the underlying emitter region
109
.
An n-type polysilicon emitter contact region
111
is selectively formed on the SiO
2
layer
110
to be contacted with the emitter region
109
through the window
124
in the transistor region
130
. The emitter contact region
111
is doped with arsenic (As). The As-doped region
111
serves as a diffusion source of the n-type impurity As during the thermal diffusion process of forming the n-type emitter region
109
.
An n-type polysilicon resistor layer
121
is selectively formed on the SiO
2
layer
110
in the resistor region
131
. The resistor layer
121
also is doped with As, and serves as the resistor as shown in FIG.
1
. The doping concentration of As in the layer
121
is set at a value that enables a wanted resistance.
A SiO
2
layer
112
and a Boro-Phospho-Silicate Glass (BPSG) layer
113
are successively formed on the SiO
2
layer
110
to cover the n-type polysilicon emitter contact
111
and the n-type polysilicon resistor layer
121
.
A contact hole
125
is formed to vertically penetrate the BPSG layer
113
, the SiO
2
layer
112
, and the SiO
2
layer
110
in the transistor region
130
. The contact hole
125
is located above the extrinsic base region
107
and exposes the underlying region
107
.
A contact hole
126
is formed to vertically penetrate the BPSG layer
113
and the SiO
2
layer
112
in the transistor region
130
. The contact hole
126
is located above the emitter contact region
111
and exposes the underlying region
111
.
Two contact holes
123
are formed to vertically penetrate the BPSG layer
113
and the SiO
2
layer
112
in the resistor region
131
. The contact hole
123
are located above the resistor layer
121
and exposes the underlying layer
121
.
Barrier metal layers
114
are selectively formed in the contact holes
123
,
125
,
126
to cover the sides and bottoms of the holes
123
,
125
,
126
, respectively. The layer
114
in the hole
125
is contacted with the extrinsic base region
107
. The layer
114
in the hole
126
is contacted with the emitter contact region
111
. The two layers
114
in the hole
123
are contacted with the polysilicon resistor layer
121
, respectively.
Tungsten (W) layers
115
are selectively formed on the corresponding barrier metal layers
114
in the contact holes
123
,
125
,
126
, respectively. The W layers
115
bury the corresponding holes
123
,
125
, and
126
. In other words, the W layers
115
serve as conductor plugs, respectively.
Wiring or interconnection layers
116
made of an alloy of AlSiCu are selectively formed on the corresponding barrier layers
114
and the corresponding W layers
115
, respectively.
The conventional semiconductor device of
FIG. 2
is fabricated in the following way:
First, as shown in
FIG. 3A
, the n-type single-crystal Si epitaxial layer
104
, the n-type buried layer
102
, the p-type insulating layer
103
, the field oxide layer
105
of SiO
2
, the n
+
-type collector connection region
106
, the p-type extrinsic base region
107
, and the p-type intrinsic base region
108
, and the n-type emitter region
109
are formed on the p-type single-crystal Si substrate
101
with the use of known process steps.
Then, the SiO
2
layer
110
with a thickness of 150 to 400 nm is formed on the field oxide layer
105
and the exposed epitaxial layer
104
by using, for example, a Chemical Vapor Deposition (CVD) process.
The contact window
124
is formed in the SiO
2
layer
110
by using photolithography and dry etching processes, thereby exposing the underlying the intrinsic base region
108
.
Subsequently, a polysilicon layer (not shown) with a thickness of approximately 330 nm is formed on the SiO
2
layer
110
by using, for example, a Low-Pressure CVD process. This polysilicon layer may be formed by a sputtering process. In this case, this layer becomes amorphous. This means that the polysilicon layer may be replaced with an amorphous silicon layer.
A part of the polysilicon layer thus formed, which serves as the impurity source for the formation process of the n-type emitter region
109
, is selectively doped with As by an ion-implantation process at an acceleration energy of 50 keV to 100 keV with a dose of 1×10
16
atoms/cm
2
. Further, while masking the As doped part of the polysilicon layer, the remaining part of the polysilicon layer is selectively doped with boron (B) by an ion-implantation process at an acceleration energy of 30 keV with a dose of 6×10
14
atoms/cm
2
. The acceleration energy and the dose of the second ion-implantation process are determined to realize a wanted, predetermined sheet resistance and a wanted, predetermined contact resistan
Duong Hung Van
Foley & Lardner
NEC Corporation
Picard Leo P.
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