Semiconductor device with reduced terminal input capacitance

Details Semiconductor device with reduced terminal input capacitance Semiconductor device with reduced terminal input capacitance

2005-08-23

2005-08-23

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S185240

Reexamination Certificate

active

06934204

ABSTRACT:
A P-channel MOS transistor is provided between a terminal and an SVIH detection circuit for performing test mode detection. The P-channel MOS transistor is rendered non-conductive when a potential supplied to the terminal that is used commonly for signal input during the test setting and the normal operation is a power-supply potential EXTVDD or below. The SVIH detection circuit detects that a test mode is to be set when the potential at the terminal becomes higher than a prescribed potential. During the normal operation, the terminal is disconnected from the SVIH detection circuit so that the input capacitance of the terminal can be made to be about the same as that of another input terminal, and a high speed operation becomes possible. Moreover, there is no need to take into account the parasitic capacitance of an interconnection line leading to the SVIH detection circuit.

REFERENCES:
patent: 4812680 (1989-03-01), Kawashima et al.
patent: 4833341 (1989-05-01), Watanabe et al.
patent: 4937700 (1990-06-01), Iwahashi
patent: 5694364 (1997-12-01), Morishita et al.
patent: 7-74318 (1995-03-01), None
patent: 10-21699 (1998-01-01), None
patent: 2000-887 (2000-01-01), None

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