Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2002-03-06
2004-04-06
Pert, Evan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S687000, C257S778000
Reexamination Certificate
active
06717279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit device having a structure, in which a semiconductor chip and an interposer substrate are integrally coupled by a flip chip connection, and a fabrication process of the circuit device.
2. Description of the Related Art
Currently, circuit devices, such as IC (Integrated Circuit) and so forth, have been fabricated as independent chip parts, and are used in various electronic equipments. Such circuit device has a structure, in which a large number of lead terminals are arranged on a circumference of a semiconductor chip of a semiconductor circuit having large number of connection pads, the lead terminals are individually connected with the connection pads of the semiconductor chip by bonding wire, and inside portions of the semiconductor chip and the lead terminals are sealingly embedded in resin member.
In the circuit device of the construction set forth above, since a large number of lead terminals are projected outside of an outer periphery portion of the resin member, data communication can be established between the printed circuit on a printed circuit board (PCB) and a semiconductor circuit of the circuit device by mounting the circuit device on an upper surface of the PCB and connecting the lead terminals with the printed circuit.
However, in the recent years, downsizing and increasing of integration degree of the circuit device is in progress to cause increasing of number and density of the lead terminals. This causes difficulty in accurately connecting the lead terminals of the circuit device to the printed circuit on the PCB at user level. Furthermore, fine lead terminals lack strength to easily cause breakage of the lead terminals in handling at user level to spoil the circuit device.
In order to solve the foregoing problem, a semiconductor package as the circuit device of BGA (Ball Grid Array) structure has been developed. In the semiconductor package of the BGA structure, connection terminals are formed as spherical solder bump, which are, arranged entire area of a lower surface of the device as two-dimensional array. Therefore, arrangement density of the lead terminals can be lowered and breakage of the lead terminals is hardly caused.
One example of the conventional circuit device of BGA structure will be discussed hereinafter with reference to FIG.
15
. It should be noted that
FIG. 15
is a diagrammatically illustrated section showing an internal structure of the semiconductor package as the circuit device. On the other hand, for simplification of disclosure, up and down direction on the drawing is expressed as up and down direction of the device, simply.
As shown in
FIG. 15
, the semiconductor package
1
exemplifying the circuit device has a semiconductor chip
2
consisted of a semiconductor circuit integrated at high density. The semiconductor chip
2
is mounted on the upper surface of the interposer substrate
3
. The semiconductor chip
2
is formed with a large number of connection pads (not shown) on the lower surface. On the other hand, the interposer substrate
3
is formed with a large number of connection pads (not shown) on both of the upper surface and the lower surface.
In greater detail, the interposer substrate
3
is formed with a large number of connection pads at the center portion of the upper surface at positions corresponding to the connection pads of the semiconductor chip
2
at high density, and large number of connection pads is formed over substantially entire area at low density. Then, the interposer substrate
3
is formed into a multi-layer structure and large number of printed circuits and through holes is formed in the upper surface, the lower surface and inside. A large number of connection pads on the upper surface and the lower surface are appropriately connected through the printed circuits and the through holes.
On each of these connection pads, a solder bump
4
is mounted. The connection pad on the lower surface of the semiconductor chip
2
and the connection pad on the upper surface of the interposer substrate
3
are mechanically connected by a solder bump
4
for electrical connection. It should be noted that within intervals between the solder bumps
4
, an under-fill resin
5
of epoxy resin is filled. By the under-fill resin
5
, mechanical connection between the lower surface of the semiconductor chip
2
and the upper surface of the interposer substrate
3
is reinforced.
Furthermore, in the semiconductor package
1
exemplified herein, sidewall form metallic stiffener
6
is engaged on the outer peripheral portion of the upper surface of the interposer substrate
3
. On the upper surfaces of the stiffener
6
and the semiconductor chip
2
, a top plate form metallic heat spreader
7
is bonded by a metal paste
8
.
In the semiconductor package
1
of the construction set forth above, the semiconductor circuit is integrated on the semiconductor chip
2
at high density, and the connection pads are arranged on the semiconductor chip
2
at high density. On large number of connection pads on the upper surface of the interposer substrate
3
of the same arrangement, solder bumps
4
are connected individually. A large number of connection pads on the upper surface of the interposer substrate
3
are appropriately connected to a large number of connection pads arranged on the lower surface thereof at low density.
The conventional fabrication process of the semiconductor package
1
of the structure set forth above will be discussed briefly. At first, as various parts forming the semiconductor package
1
, the semiconductor chip
2
, the interposer
3
, the stiffener
6
, the heat spreader
7
and so forth are fabricated with respectively predetermined structures.
Next, the stiffener
6
is bonded on the outer periphery portion on the upper surface of the interposer substrate
3
, and the semiconductor chip
2
is bonded on the center portion by the solder bump
4
by bonding connection. Then, the entire interposer substrate
2
with the stiffener
6
and the semiconductor chip
2
is washed by flux washing and dried. Then, O
2
plasma process is performed. Within gaps between the interposer substrate
3
and the semiconductor chip
2
, epoxy resin to be under-fill resin
5
is filled and cured to form the under-fill resin
5
.
Then, the head spreader
7
is bonded on the upper surface of the semiconductor chip
2
by the metal paste
8
and also bonded on the stiffener
6
by an bonding agent
9
, such as epoxy resin or the like. Finally, for each of large number of connection pads on the lower surface of the interposer substrate
3
, the solder bumps
4
are loaded to complete the semiconductor package
1
.
Upon fabrication of the semiconductor package
1
set forth above, the under-fill resin
5
is filled in order to improve mechanical connection strength of the semiconductor chip
2
and the interposer substrate
3
. As a method of implantation of the under-fill resin
5
, a liquid state resin is supplied from peripheral edge of the semiconductor chip by means of a dispensing nozzle mounting a syringes stocking the liquid state resin for making the high viscosity epoxy resin to penetrate into fine gaps between the semiconductor chip
2
and the interposer substrate by capillary phenomenon. However, long period is required for operation to make the liquid state resin to penetrate and a long required for curing the liquid state resin becomes longer than that of transfer molding using a tablet resin to degrade production efficiency. Furthermore, by penetration depending upon capillary phenomenon, internal void as a space not filled with the resin can be caused to make it difficult to enhance reliability of the package.
On the other hand, in the foregoing semiconductor package
1
is separately fabricated the interposer substrate
3
and the stiffener
6
and is then bonded. On the stiffener
6
, the heat spreader
7
is bonded by epoxy resin. Therefore, number of process steps in fabrication and number of component part
Cruz Lourdes
NEC Corporation
Pert Evan
Whitham Curtis & Christofferson, P.C.
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