Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2000-08-01
2002-10-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S200000
Reexamination Certificate
active
06469923
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device utilizing a capacitor as a programming element. More specifically, the present invention relates to the structure of a programming circuit in a dynamic semiconductor memory device including a memory cell having a capacitor.
2. Description of the Background Art
In a semiconductor device, programming circuits are employed for various applications. In a semiconductor memory device, for example, programming circuitry is employed for setting operation modes such as a fast page mode and an EDO (extended data output) mode, setting a word structure (×8 or ×16) and the like in a DRAM (dynamic random access memory). In order to finely adjust a resistance value for generating a reference voltage, a fusible link element is employed as the programming element.
In the semiconductor memory device, a defective address programming circuit for storing a defective address is employed in order to repair a defective memory cell. When a defective address is designated, an addressed normal memory cell is replaced with a redundant memory cell.
In such a programming circuit, a fusible link element (fuse element) is generally employed. An energy beam such as a laser beam is employed for programming (blowing
on-blowing) the fuse element. When such a fuse element is employed, a post-step of cleaning or the like is necessary for preventing blown fragments from scattering around the portion irradiated with the energy beam after blowing (laser blowing), resulting in a relatively long time for the program.
When fuse elements are arranged in high density in a high density/highly integrated semiconductor device, an adjacent fuse element is partially damaged due to misalignment of the laser beam, to cause difficulty in correct programming.
Further, the fuse elements to be blown are incompletely blown due to misalignment of the laser beam, to result in incorrect programming.
When the fuse elements are defective address programming elements for repairing defective memory cells, the number of the fuse elements to be blown is increased to result in a high possibility of erroneous programming. Such erroneous programming reduces the yield of the products.
In addition to the aforementioned fusible link elements, programming elements include an element called an anti-fuse. In this anti-fuse, a capacitor insulation film is subject to dielectric breakdown depending on information to be stored, for performing programming in accordance with conduction
on-conduction of the capacitor.
FIG. 35
schematically illustrates the structure of a conventional anti-fuse circuit. Referring to
FIG. 35
, the anti-fuse circuit includes a programmable capacitor (anti-fuse)
900
having an electrode node coupled to a node
902
, a decoupling transistor
903
coupling a second electrode node of the programmable capacitor
900
to a node
904
, an invertor
906
determining the program state of the programmable capacitor (hereinafter simply referred to as anti-fuse)
900
in accordance with the signal potential on the node
904
and outputting a signal FR indicating the result of the determination, a p-channel MOS transistor
908
charging the node
904
to the level of a power supply voltage Vcc in response to a trigger signal ZT, and n-channel MOS transistors
910
and
912
serially connected between the node
904
and a ground node. MOS transistor
910
receives a program signal AD at its gate, while MOS transistor
912
receives the signal FR outputted from invertor
906
at its gate.
The anti-fuse circuit further includes a p-channel MOS transistor
914
charging the node
904
to the level of the power supply voltage Vcc in accordance with the output signal FR from the invertor
906
and an n-channel MOS transistor
916
discharging the node
904
to the level of a ground voltage in accordance with a reset signal RST.
A high voltage (e.g., 12 V) is applied to the node
902
in a program mode, while the ground voltage is applied thereto in a normal operation mode (in a determination mode and in a standby state). MOS transistor
903
receives the power supply voltage Vcc on its gate and prevents the high voltage applied to the node
902
from being applied to the remaining circuit elements in programming of the anti-fuse
900
. Operations of the anti-fuse circuit shown in
FIG. 35
are now briefly described.
A programming operation for the anti-fuse
900
is described with reference to FIG.
36
A. In the programming operation mode, the trigger signal ZT is set high and the MOS transistor
908
is held in a non-conductive state. The signal AD is set at a prescribed voltage level in accordance with programming information. Referring to
FIG. 36A
, the signal AD is set high in order to put (blow) the anti-fuse
900
in a conductive state. In an initial state, the node
904
is precharged to a high level and the signal FR from the invertor
906
is set low due to initialization of the trigger signal ZT. In response to the low-level signal FR, MOS transistor
914
is rendered conductive and the node
904
is held at a low level.
In the programming operation mode, the reset signal RST is set high and the MOS transistor
916
is rendered conductive. The node
904
is discharged to the ground voltage level and the signal FR rises to a high level. In response to the rise of the signal FR, MOS transistor
914
is rendered non-conductive while MOS transistor
912
is rendered conductive, and the node
904
is coupled to the ground node through the MOS transistors
910
and
912
. While the reset signal RST is at the high level, the level of the voltage supplied to the node
902
is increased. Since the reset signal RST is at the high level, an increase of the voltage level of the node
904
due to capacitive coupling of the anti-fuse
900
is prevented when the voltage for the node
902
is raised, and the signal FR maintains the high level.
When the reset signal RST is set low, a high voltage for programming is applied to the node
902
. A high voltage is applied across the anti-fuse
900
due to the voltage of the node
902
, to cause a dielectric breakdown of a capacitor insulation film (the signal AD is at a high level). The voltage applied to the node
902
is transmitted to the node
904
to increase the voltage level thereat due to the dielectric breakdown of the anti-fuse
900
. The voltage of the node
904
is determined by the ratio of the resistance of the anti-fuse
900
to the combined channel resistance of the transistors
910
and
912
. When the voltage of the node
904
exceeds the input logic threshold voltage of the invertor
906
, the signal FR lowers from the high level to a low level, the MOS transistor
912
is rendered non-conductive and the MOS transistor
914
is rendered conductive. The node
904
is charged to the level of the power supply voltage Vcc through the MOS. transistor
914
. The decoupling transistor
903
transmits a voltage Vcc−Vth, where Vth represents the threshold voltage of the decoupling transistor
903
. Thus, the flow of a current from the node
902
to the node
904
through the anti-fuse
900
is cut off to complete the programming of the anti-fuse
900
.
When the signal AD is set low in the programming operation mode, the MOS transistor
910
is held in a non-conductive state. When the node
904
is discharged to the ground voltage level through the MOS transistor
916
by the reset signal RST, the signal FR rises to a high level for driving the MOS transistor
914
to a non-conductive state. When the reset signal RST falls to a low level, therefore, all MOS transistors
908
,
910
,
914
and
916
are rendered non-conductive and hence the node
904
enters a floating state. When a high voltage for programming is applied to the node
902
in this state, the high voltage for programming is transmitted from the node
902
to the node
904
through the MOS transistor
903
by capacitive coupling though the anti
McDermott & Will & Emery
Nelms David
Tran M.
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