Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-03
2004-07-20
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S603000, C257S630000
Reexamination Certificate
active
06765266
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 2001-374256 filed on Dec. 7, 2001, the contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device with a peripheral portion for withstanding a surge voltage.
BACKGROUND OF THE INVENTION
Conventionally, a semiconductor device including an IGBT or the like has a peripheral portion for withstanding a surge voltage (e.g., JP-A-10-163482).
FIG. 5
shows a cross sectional view of such a semiconductor device with an IGBT. IGBT elements (hereinafter referred to as a cell portion) are formed on a right side of the device in
FIG. 5. A
peripheral portion for withstanding a surge voltage caused by power surge (hereinafter referred to as a peripheral voltage withstand portion) is formed on a left side of the cell portion.
A semiconductor substrate
101
includes a p+ type layer
101
A and an n− type layer
101
B disposed on the p+ type layer
101
A. A side of the p+ type layer
101
A of the semiconductor substrate
101
is a reverse surface
101
a
on which a collector electrode
102
is formed, and a side of the n− type layer
101
B is a main surface
101
b.
In the peripheral voltage withstand portion, a peripheral p type well region
113
is formed on a surface portion of the n− type layer
101
B. A p type well region
114
, which is shallower than the peripheral p type well region
113
, is formed at the most peripheral position of the peripheral p type well region
113
so as to overlap therewith. Hereinafter, the p type well region
114
is referred to as a most peripheral well region. In a most peripheral position of the semiconductor device, an n+ region
115
is formed on the surface portion of the n− layer
101
B to surround the cell portion and the most peripheral well region
114
.
A LOCOS oxide film
116
is formed on the main surface
101
b
of the n− type layer
101
B and a plurality of field plate rings
117
a
-
117
e
formed thereon are disposed from the peripheral p type well region
113
to an edge of the n+ type region
115
on a side of the cell portion. Zener diodes
118
a
-
118
d
made of poly-silicon or the like are disposed on the field plate rings
117
a
-
117
e
. Each of the zener diodes
118
a
-
118
d
is disposed between and electrically contacts adjacent field plate rings
117
a
-
117
e
. The field plate ring
117
a
is electrically connected to a gate electrode
119
, and the field plate ring
117
e
is electrically connected to the n+ region
115
.
In the above semiconductor device, each of the field plate rings
117
a
-
117
e
and each of the Zener diodes
118
a
-
118
d
are alternatively disposed at predetermined intervals in the cell portion to a periphery of the cell portion. Therefore, in the n− type layer
101
B, an electric potential is distributed uniformly in a direction from the peripheral p type well region
113
to the most peripheral well region
114
when a surge voltage is applied to the semiconductor device. The surge voltage applied to the semiconductor device is distributed along a surface of the n− type layer
101
B, and therefore an electric field is prevented from being locally concentrated.
Further, in the above semiconductor device, the most peripheral well region
114
with a shallow and relatively low impurity concentration is located at a periphery of the peripheral p type well region
113
, and the field plate ring
117
a
located at the innermost side of the field plate rings
117
a
-
117
e
protrudes from a peripheral edge
14
a
E of the most peripheral well region
114
in a peripheral direction. Accordingly, curvature of a peripheral edge of the peripheral p type well region
113
and an electric field distribution feature near the edge is improved, and local concentration of the electric field is prevented.
SUMMARY OF THE INVENTION
FIG. 6A
shows an equipotential line distribution of a cross section of the semiconductor device of
FIG. 5
calculated based on a simulation analysis.
FIG. 6B
shows an expansion view of a region B near a peripheral edge
117
a
E of the field plate ring
117
a
of FIG.
6
A. In the simulation, dV/dt is about 2 kV
s. When a reverse bias is applied to the semiconductor device, a depletion layer formed by a PN junction of the n− type layer
101
B and the peripheral p type well region
113
extends in a side of the peripheral p type well region
113
from the PN junction. Since the depletion layer extends from the peripheral p type well region
113
in a further peripheral direction thereof, the equipotential line distributes as in
FIG. 6A
based on the electric potential of the field plate rings
117
a
-
117
e.
However, as shown in
FIG. 6B
, because the peripheral edge
114
a
E of the most peripheral well region
114
separates from the field plate ring
117
a
and the field plate ring
117
b
neighboring the field plate ring
117
a
, the equipotential line extends from the most peripheral well region
114
and the peripheral p type well region
113
to the portion disposed between both field plate rings
117
a
,
117
b
along the LOCOS oxide layer
116
. Therefore, the equipotential line concentrates in a part of the LOCOS oxide film
116
under the peripheral edge
117
a
E of the field plate ring
117
a
, and an electric field intensity increases at the part of the LOCOS oxide film
116
. Accordingly, reliability of the LOCOS oxide film
116
for withstanding the surge voltage, especially a rapid surge voltage, may decrease.
It is therefore an object of the present invention to provide a semiconductor device that is capable of obviating the above problem.
It is another object of the present invention to provide a semiconductor device with an oxide film having increased reliability for withstanding surge voltage.
According to a semiconductor device of the present invention, a first semiconductor region is formed so that a peripheral edge thereof is located between a first field plate ring that corresponds to one of the field plate rings located at the innermost side thereof and a second field plate ring that corresponds to one of the field plate rings neighboring the first plate ring.
As the first semiconductor region is not completely depleted by a depletion layer, it is preferable that an edge of the depletion layer extended to the first semiconductor layer is located between or near the first field plate ring and the second field plate ring. Further, when a reduced surface field (resurf) configuration is connected to the periphery of the first semiconductor region, the peripheral edge of the first semiconductor layer can be defined by correlating it to a position located between a first field plate ring and the second field plate ring.
Accordingly, when a surge voltage is applied to the semiconductor device of the present invention, an electric field concentration at a part of the isolation film located under the first one of the field plate rings is relaxed and an electric field intensity decreases. Therefore, the reliability of the isolation film for withstanding surge voltage increases.
REFERENCES:
patent: 5324971 (1994-06-01), Notley
patent: 5475258 (1995-12-01), Kato et al.
patent: 5959345 (1999-09-01), Fruth et al.
patent: A-10-163482 (1998-06-01), None
patent: A-2002-184988 (2002-06-01), None
Kawakita Haruo
Ozeki Yoshihiko
Tokura Norihito
Tomatsu Yutaka
Denso Corporation
Munson Gene M.
Posz & Bethards, PLC
LandOfFree
Semiconductor device with peripheral portion for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with peripheral portion for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with peripheral portion for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3186491