Semiconductor device with parallel interconnects

Details Semiconductor device with parallel interconnects Semiconductor device with parallel interconnects

2008-05-13

2008-05-13

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S211000, C257S207000, C257S208000, C257S288000, C257S773000, C257S758000

Reexamination Certificate

active

11049417

ABSTRACT:
A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.

REFERENCES:
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patent: 09-148526 (1997-06-01), None
patent: 2000-174268 (2000-06-01), None
Clement H. Wann, “A Comparative Study of Advanced MOSFET Concepts”,IEEE Transactions of Electronics Devices, vol. 43, pp. 1742-1743 (1996).
“Phenomena in Graded Junction Devices”;IEEE, IRPS, p. 71, (1989).
ULSI Technology, McGraw-Hill, p. 443, (1996).

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