4. Active solid-state devices (e.g., transistors, solid-state diode
  5. Combined with electrical contact or lead
  6. Of specified configuration

Naoei Takeishi

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Pattern layout method of semiconductor device

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Semiconductor device

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Semiconductor device and pattern layout method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate

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Semiconductor device with parallel interconnects

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate

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Semiconductor device with parallel interconnects

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2384065

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