Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-06-10
2004-09-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S230030
Reexamination Certificate
active
06791877
ABSTRACT:
CLAIM OF PRIORITY
This application claims priority to Japanese Patent Application No. 2001-174978 filed on Jun. 11, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked memory semiconductor device that includes various kinds of memories, and, more particularly, the present invention relates to a combination of said stacked memories, a method for controlling those memories, and a structure for integrating those memories into a multi-chip module.
2. Description of the Background
The following documents are referenced in this specification. The documents are numbered, and hereinafter, they will be described with reference to these numbers. [“Document 1”]: LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet (Apr. 21, 2000); [“Document 2”]: Official Gazette of JP-A 299616/1991 (Official Gazette of European Patent No. 566,360, Oct. 20, 1993); [“Document 3”]: Official Gazette of JP-A 146820/1993; and [“Document 4”]: Official Gazette of JP-A 5723/2001.
Document 1 discloses a stacked semiconductor memory in which a flash memory (capacity: 32M bits) and an SRAM (capacity: 4M bits) are molded together on a stacked chip in an FBGA package. The flash memory and the SRAM share address input terminals and data I/O terminals connected to the input/output electrodes of the FBGA package respectively. However, the control terminals of the memories are independent of each other.
FIG. 17
in Document 2 shows a stacked semiconductor memory in which a flash memory chip and a DRAM chip are molded together in a lead frame package.
FIG. 1
in Document 2 shows a stacked memory in which a flash memory and a DRAM share address input terminals, data I/O terminals, as well as a control terminal connected to the input/output electrodes of the package respectively.
FIG. 1
in Document 3 shows a system comprised of a flash memory used as a main storage, a cache memory, a controller, and a CPU.
FIG. 2
in Document 4 shows a semiconductor memory comprised of a flash memory, a DRAM, and a transfer control circuit.
An examination of cellular telephones, as well as memory modules used for those cellular phones, confirms that, in each of those memory modules, a flash memory and an SRAM are mounted together in one package. Cellular phones are often provided with various functions (related to the distribution of music, games, etc.), and the size of the corresponding application programs, data, and work areas thereof are ever increasing. It is to be expected that cellular phones with larger capacity flash memories and SRAMs will soon be needed. Additionally, the recent enhancement of cellular phone functionalities may also require larger capacity memories.
Presently, a cellular phone uses a flash memory that employs so-called “NOR memory cell arrays.” The NOR flash memory employs memory cell arrays that suppress the parasitic resistance. The NOR flash memory lowers the resistance by providing one through-hole to bit line for two cells connected in parallel. This reduces the reading time to about 80 ns, which is almost equal to the reading time of a large capacity, medium access speed SRAM. On the contrary, because one through-hole to bit line must be provided for two cells, the ratio of the through-hole to bit line area to the chip area increases such that the one-bit memory cell area also increases. It has been difficult to give a large capacity to the NOR flash memory. This has been a problem.
Typical large capacity flash memories are roughly classified into two types: AND flash memories that employ the AND memory arrays and NAND flash memories that employ the NAND memory arrays. In each of these flash memories, one through-hole to bit line is formed for 16 to 128 cells, so that the flash memory can form high density memory arrays. Consequently, it is possible to reduce the one-bit area per memory cell more than that of NOR flash memories. A larger capacity can thus be given to those flash memories. On the contrary, the reading time for outputting the first data becomes about 25 &mgr;s to 50 &mgr;s, so that those flash memories can not easily match the read access speed of an SRAM.
A flash memory can keep data even when the power supply to the cellular phone (or other device) is shut off. However, power is kept supplied to an SRAM so as to hold data therein even when the power to the cellular phone is off. To hold data in an SRAM for an extended period of time, therefore, the data retention current should be minimized. Large capacity SRAMs are confronted with problems in that the data retention current increases in proportion to an increase in the capacity of the memory and the data retention current increases due to an increase in the gate leakage current. This occurs because a tunnel current flows to the substrate from a gate when the oxide insulator of the MOS transistor is thinned in a micro-machining process meant to increase the capacity of the SRAM. As a result, the data retention current increases. It has been noted that it is increasingly difficult to reduce the data retention current in larger capacity SRAMs.
To address the above-mentioned problems, the present invention preferably provides a ROM that has an increased memory capacity and the ability to read and write data quickly, as well as a RAM that has an increased memory capacity and requires reduced data retention current.
SUMMARY OF THE INVENTION
In at least one preferred embodiment, the present invention provides a semiconductor device comprising: a non-volatile memory having a first reading time; a random access memory RAM having a second reading time, which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit that is connected to and controls access to both the non-volatile memory and the random access memory; and a plurality of input/output terminals connected to the circuit.
The control circuit is preferably adapted such that at least part of the data stored in the non-volatile memory (flash memory) is transferred to the DRAM (random access memory) before operation of the device. To write data in the non-volatile memory, the data should be initially written to the RAM and then written to the non-volatile memory from the RAM between access requests from devices located outside the semiconductor device. In addition, the control circuit may be adapted to control such that refreshment of the DRAM is hidden from external when the RAM is a DRAM.
REFERENCES:
patent: 5530673 (1996-06-01), Tobita et al.
patent: 5650976 (1997-07-01), McLaury
patent: 6029046 (2000-02-01), Khan
patent: 6324103 (2001-11-01), Hiraki et al.
patent: 6484270 (2002-11-01), Odani
patent: 0 566 306 (1993-04-01), None
patent: 7-146820 (1994-04-01), None
patent: 2001-5723 (1999-06-01), None
Sharp Corporation, “LRS1337 Stacked Chip 32M Flash Memory and 4M SDRAM” Data Sheet, 1999, pp. 1-24.
Ayukawa Kazushige
Miura Seiji
A. Marquez, Esq. Juan Carlos
Dinh Son T.
Fisher Esq. Stanley P.
Reed Smith LLP
Renesas Technology Corporation
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