Semiconductor device with multilayer silicon oxide silicon nitri

Details Semiconductor device with multilayer silicon oxide silicon nitri Semiconductor device with multilayer silicon oxide silicon nitri

1988-03-15

1990-03-06

LaRoche, Eugene R.

357 51, 357 54, H01L 2978, H01L 2702, H01L 2934

Patent

active

049070460

ABSTRACT:
A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).

REFERENCES:
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patent: 4536947 (1985-08-01), Bohr et al.
patent: 4768080 (1988-08-01), Sato
patent: 4805147 (1989-02-01), Yamanaka et al.
Characterization of Thermally Oxidized n+ Polycrystalline Silicon, by Faraone, et al., IEEE Transactions on Electron Devices, vol. ED-32, No. 3, Mar. 1985, pp. 577-583.

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