Process for making metal-polysilicon double-layered gate

Details Process for making metal-polysilicon double-layered gate Process for making metal-polysilicon double-layered gate

Filed on

1989-05-04

Date issued

1990-03-13

Examiner

Hearn, Brian E.

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437193, 437194, 437 41, 437228, H01L 21283

Type

Patent

Status

active

Patent number

049083325

Description

ABSTRACT:
A process for reducing gate sheet resistance in VSLI devices employs planarization and metal refilling to produce a gate of layers of polysilicon and pure metal. The polysilicon underlayer maintains the characteristics of a polysilicon gate and the metal layer reduces the gate sheet resistance. The process includes the etching back of the planarized dielectric (6) to expose the top surface of the polysilicon gate (3), the etching of the polysilicon to form a groove, and the filling of the groove with a metal, e.g. W, by selective or blanket CVD.

REFERENCES:
patent: 4514233 (1985-04-01), Kawabuchi
patent: 4616401 (1986-10-01), Takeuchi
patent: 4728620 (1988-03-01), Jench
patent: 4755478 (1988-07-01), Abernathey et al.

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