Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2002-07-24
2004-07-20
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S650000, C257S774000
Reexamination Certificate
active
06765283
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2001-223328 filed on Jul. 24, 2001, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, more specifically, to a semiconductor device using an insulating film at least in a part of an interlayer dielectric film and a method for fabricating the same, the insulating film has a relative dielectric constant lower than that of silicon nitride and contains an impurity capable of detecting an etching end point.
2. The Related Art
With miniaturization and high integration of semiconductor devices, scaling down of internal interconnects and realization of multilayer internal interconnects have been proceeding. According with this, demands for planarization techniques of interlayer dielectric films and micro-fabrication such as dry etching have been more severe. Then, to meet these demands, a buried interconnect technique has been studied.
In the buried interconnect technique, a trench for an interconnect pattern is formed in an interlayer dielectric film, the inside of the trench is buried with an interconnect material, and then the interconnect material other than the inside of the trench is removed to leave the interconnect material only inside the trench. Thus, the interconnect portion is formed in a shape of burying it in the interlayer dielectric film. Accordingly, it is more advantageous in the planarization of the interlayer dielectric film than a traditional multilevel metallization technique, allowing a copper (Cu) interconnect, which has been difficult in processing by traditional RIE (Reactive Ion Etching). The Cu interconnect has low resistance and high reliability, thus attracting attention as a next generation interconnect material.
In such the buried interconnect technique, an etching stopper film is deposited in an interlayer dielectric film in general. Etching is performed under the condition that a selected ratio is great to this etching stopper film, whereby a trench and a connection hole for buried interconnect are formed in the interlayer dielectric film. As the etching stopper film, a silicon nitride film is used in the case of an SiO
2
based interlayer dielectric film, for example.
However, the silicon nitride film has a relative dielectric constant of about seven, significantly greater than that of SiO
2
systems, about four, increasing the relative dielectric constant of the entire interlayer dielectric film. Consequently, it is known to generate defects leading to signal delay or an increase in power consumption.
Then, Japanese Unexamined Patent Publication No. HEI 10(1998)-150105, for example, has been proposed a method of using an organic low dielectric constant film as an etching stopper film for the purpose of reducing the capacitance of an interlayer dielectric film, the organic low dielectric constant film has a relative dielectric constant lower than that of a silicon nitride film and contains fluorine.
According to this method, as shown in
FIG. 3A
, an underlayer insulating film
12
comprised of silicon oxide is deposited as a part of an interlayer dielectric film on a semiconductor substrate
11
by CVD using mono-silane and an oxygen gas as source gas. An organic low dielectric constant film
13
having a relative dielectric constant lower than that of silicon nitride is deposited thereon by spin coating, for example. An insulating film
14
comprised of a silicon oxide film as similar to the underlayer insulating film
12
and an organic low dielectric constant film
15
as similar to the organic low dielectric constant film
13
are deposited thereon.
Subsequently, a resist film (not shown) is deposited on the organic low dielectric constant film
15
. The resist film is patterned by a photolithography process to form an opening over an area for forming a trench for buried interconnect. The resist film is used as a mask to etch the organic low dielectric constant film
15
as shown in FIG.
3
B. Then, the insulating film
14
is etched to form a trench
16
for buried interconnect in the organic low dielectric constant film
15
and the insulating film
14
.
After that, as shown in
FIG. 3C
, an interconnect layer
17
is formed inside the trench
16
by damascene.
Subsequently, as shown in
FIG. 3D
, an insulating film
18
comprised of a silicon oxide film as similar to the underlayer insulating film
12
and the insulating film
14
is deposited over the entire surface of the organic low dielectric constant film
15
and the interconnect layer
17
.
A resist film (not shown) is deposited on the insulating film
18
. The resist film is patterned by the photolithography process to form an opening over an area for forming a connection hole to the interconnect layer
17
. As shown in
FIG. 3E
, the resist film is used as a mask to etch the insulating film
18
, and a connection hole
19
reaching the interconnect layer
17
is formed in the insulating film
18
.
Furthermore, as shown in
FIG. 3F
, a plug
20
comprised of tungsten, for example, is buried inside the connection hole
19
.
After that, an upper interconnect is formed on the insulating film
18
in a pattern of connecting to the plug
20
.
However, as described above, when the organic low dielectric constant film containing relatively plenty of fluorine is used as the etching stopper film for the purpose of decreasing interlayer capacitance, a problem is arisen that reaction products are generated greatly in the bottom of the trench and the connection hole while etching the interlayer dielectric film and the reaction products increase the electric resistance in interconnection.
SUMMARY OF THE INVENTION
The invention was made in view of the problems. The purpose is to provide a semiconductor device and a method for fabricating the same, the semiconductor device is capable of reducing interlayer capacitance, terminating etching by controlling endpoint detection highly accurately, not by etching stop utilizing a high selected ratio, and performing etching with fewer reaction products, and has interconnections of low electric resistance.
According to the invention, provided is a semiconductor device comprising:
an underlayer interconnect layer;
an interlayer dielectric film formed with a connection hole reaching the underlayer interconnect layer; and
an upper interconnect layer buried in the connection hole,
wherein the interlayer dielectric film includes an insulating film containing an impurity for detecting a first etching end point, a first insulating film, an insulating film containing an impurity for detecting a second etching end point and a second insulating film, these four films being laminated in this order.
Additionally, according to the invention, provided is a method for fabricating a semiconductor device comprising the steps of:
forming an insulating film containing an impurity for detecting a first etching end point, a first insulating film, an insulating film containing an impurity for detecting a second etching end point, and a second insulating film on an underlayer interconnect layer in this order;
forming a connection hole by etching, the connection hole reaching from the surface of the second insulating film to the insulating film containing the impurity for detecting the first etching end point;
forming a protection film in the bottom of the connection hole;
forming a trench by etching, the trench reaching from the surface of the second insulating film to the insulating film containing the impurity for detecting the second etching end point and connecting with the connection hole; and
removing the protection film, and thereafter, burying a conductive material in the connection hole and the trench, thereby forming an upper interconnect layer.
These and other objects of the present application will become more readily apparent from the detailed description given her
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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