Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-23
2002-03-19
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S207000
Reexamination Certificate
active
06359297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which movement of positive ions to a circuit element region can be prevented.
2. Description of the Related Art
In a semiconductor memory device, a ground wiring line is arranged in the neighbor of a cell block to stabilize a ground level to memory cells. The memory cells and a high potential wiring line are present in the neighbor of the ground wiring line.
FIG. 1
is a cross sectional view of a conventional semiconductor memory device in the neighbor of a memory cell block. In
FIG. 1
, first and second high potential wiring lines
123
and
124
and the cell blocks are in the neighbor of a ground wiring line
112
and are formed on an interlayer
151
. When the semiconductor memory device is used in the environment of the temperature of about 85° C. and the humidity of about 70%, positive ions are generated for the influence of very small quantity of moisture and are attracted to the ground wiring line
112
. The positive ions are attracted to the ground wiring line or the memory cells in the neighbor of the ground wiring line while diffusing toward the ground wiring line
112
. Thus, the charge is collected and stored in the ground wiring line or diffusion layers of the memory cells. As a result, current flows between the ground wiring line and the cells to cause an erroneous operation.
In conjunction with the above description, a semiconductor device is described in Japanese Laid Open Patent Application (JP-A-Showa 59-228753). In this reference, a conductive wiring layer is formed above a silicon film as a resistance element to cover a junction section between a high resistance portion of the silicon film and a low resistance portion. A passivation film is formed on the conductive wiring layer.
Also, a semiconductor device is described in Japanese Laid Open Patent Application (JP-A-Heisei 4-162660). In this reference, a main portion of a high resistance element is surrounded by an insulating film, and a pair of electrodes are provided above and below the high resistance element and are connected to a wiring layer supplied with a predetermined voltage.
Also, a semiconductor device is described in Japanese Patent No. 2,667,432. In this reference, a positive bias is applied to a semiconductor substrate. An element region is formed in a well region which is formed in the semiconductor substrate. An insulating film is formed to cover the element region. A wiring line is formed on the insulating film to cover the element region and is set to a predetermined potential.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor device in which an erroneous operation due to a positive ion can be prevented.
In order to achieve an aspect of the present invention, a semiconductor device includes an interlayer formed to cover a semiconductor substrate, a circuit element, a preventing diffusion region, a power supply line and a ground line. The power supply line is formed on the interlayer to supply a positive voltage to the circuit element. The ground line is formed on the interlayer on an opposite side to the circuit element with respective to the power supply line. The circuit element is formed in a surface portion of a semiconductor substrate. The preventing diffusion region is formed in a surface portion of the semiconductor substrate in correspondence to the power supply line, and is applied with a predetermined positive voltage.
Here, the predetermined positive voltage may be equal to or lower than the positive voltage supplied from the power supply line.
Also, the semiconductor device may include a plurality of the preventing diffusion regions applied with the predetermined positive voltages which are different.
Also, it is preferable that the preventing diffusion region is provided substantially directly below the power supply line.
In addition, the semiconductor device may be a semiconductor memory device and the circuit element may be a memory cell. In this case, a memory cell transistor may be formed in the interlayer.
In order to achieve another aspect of the present invention, a semiconductor device includes a circuit element, an interlayer, a ground line, a power supply line, and a diffusion region. The circuit element is formed in a surface portion of a semiconductor substrate. The interlayer is formed to cover the semiconductor substrate. The ground line is biased to a ground potential. The power supply line is formed on the interlayer on the side of the circuit element from the ground line to generate a first electric field toward the ground line in the interlayer. The diffusion region formed in a surface portion of the semiconductor substrate to generate a second electric field toward the ground line in the interlayer such that a movement of a positive ion toward the circuit element is prevented by the first and second electric fields in the interlayer.
Here, the diffusion region may be provided in correspondence to the power supply line. Especially, it is preferable that the diffusion region is provided substantially directly below the power supply line.
Also, when a predetermined positive voltage is applied to the diffusion region, the predetermined positive voltage may be equal to or lower than a positive voltage supplied from the power supply line.
Also, the semiconductor device includes a plurality of the diffusion regions applied with the predetermined positive voltages which are different.
Also, the semiconductor device is a semiconductor memory device and the circuit element is a memory cell. In this case, a memory cell transistor may be formed in the interlayer.
REFERENCES:
patent: 5847430 (1998-12-01), Hidaka
patent: 6118158 (2000-09-01), Kim
patent: 59-228753 (1984-12-01), None
patent: 4-162660 (1992-06-01), None
patent: 2667432 (1997-06-01), None
Nagata Takami
Yamaguchi Satoshi
NEC Corporation
Thomas Tom
Tran Thien F
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